The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic pathfinding initiatives in holistic co-optimization across the product stack from system architecture to silicon as we extend Design Technology Co-Optimization (DTCO) to System Technology Co-Optimization (STCO).

Your responsibilities may include, but not be limited to:

• Establish test cases for 3D-IC STCO representing internal and external products
• Test Chips validation of 3D-IC technology and methodology
• Design analysis and feedback for 3D silicon and packaging technologies development
• Development of 3D-IC construction and verification methodology, including evaluation and feedback tool flows and methodologies, TFM, and EDA capabilities
• Collaboration with the product teams to identify critical product characteristics and target-setting requirements.
• Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation

Important behavioral attributes:

• Self motivated, out of the box thinker
• Effective team player with continuous learning mindset
• Experience working with cross functional and cross site teams

Qualifications

Minimum Qualifications
Bachelor's degree in Electrical, Computer Engineering or similar discipline with 10 or more years of professional work experience OR a Master's degree in Electrical, Computer Engineering or similar discipline with 8 or more years of professional work experience in the following areas:

• IP/SoC physical design optimization and methodologies for optimal Performance, Power, Area and Cost (PPAC).
• Experience driving physical design EDA tools, design reference/sign-off flows in advanced process technologies, and EDA vendor engagement.
• Low-power and multiple clock domain design.
• Scripting skills using a programming language such as Python, TCL

Preferred requirements

• Reference design and TFM for STCO/3D-IC
• Power management design methodologies, validation of Power Distribution Networks (PDN), IR, EM and thermals.
• 3D Silicon and 3D packaging technologies.
• Experience with ARM-based IP PPAC optimization.
• Design for Test (DFT) and Design for Debug (DFD).
• Product design co-optimization and productization across market segments.
• Logic design using SystemVerilog.
• Standard cell library and memory architecture

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.