21 days old

3D-IC STCO Senior SOC/Physical Design Architect

Intel
Hillsboro, OR 97123
  • Job Code
    JR0215419
Job Description

The future of Moore's Law: 3D-IC STCO. https://3dic-conf.org/

The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of technologies for 2025 and beyond, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and EDA Eco-System

Your responsibilities may include, but not be limited to:

  • Establish 3DIC Test Cases across market segments
  • Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities
  • Test Chips validation of 3DIC technology and methodology
  • Design analysis and feedback for 3D silicon and packaging technologies development
  • Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
  • Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation
  • Experience working with cross functional and cross site teams. Effective team player with continuous learning mindset

Important behavior traits:

  • Creative, self-motivated, independent thinker with excellent analytical and problem-solving skills.
  • Verbal/written communication skills


Qualifications

Minimum Qualifications

 PhD degree in Electrical or Computer Engineering or a Master's in Electrical, Computer Engineering with 10+ years of work experience

Direct hands-on experience in the following areas:

  • Experience driving Physical Design EDA tools, design reference/sign-off flows and EDA vendor engagement
  • Design Methodologies for optimal Performance Power Area Cost (PPAC) in advanced technologies
  • Experience with test chip designs and/or product designs
  • Low-power design and Multiple clock domain design
  • Scripting skills using a programming language such as Python, TCL

Preferred requirements

  • 3D Silicon and 3D packaging technologies
  • Reference design and TFM for STCO/3D-IC
  • Power Management Design Methodology and Validation Power Distribution Network (PDN), IR/EM, Thermals
  • Experience with ARM-based IP PPA optimization
  • Design for Test (DFT) and Design for Debug (DFD)
  • Product design co-optimization and productization across market segments
  • Logic design using System Verilog
  • Standard Cell Library and Memory Architectures
  • Circuit design and silicon technology.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-06 Expires: 2022-06-06

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3D-IC STCO Senior SOC/Physical Design Architect

Intel
Hillsboro, OR 97123

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