16 days old

AI/ML Logic Design Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

In this position, you will be a member of a Soft IP design team involved in exciting new development work in Artificial Intelligence. You will be working on Neural Accelerator IP design which is an inference engine designed for low power audio and vision use cases like speech recognition, noise suppression, Speaker ID, Face detect, Touch to speech etc and incorporates stringent power and performance KPI requirements.

Responsibilities will include but not limited to:

  • Taking technical specifications through the micro-architecture and the design process (RTL, synthesis, timing convergence. etc).

  • Working on Power estimation and optimization methods.

  • As a staff engineer, you will be expected to provide technical leadership to the junior team members and drive adoption of new design methodologies to improve quality of the designs.

  • You will be interfacing closely with Architects/Micro-Architects, Designers, Validation and TFM engineers to deliver high quality designs.

  • Require experience in developing micro-architecture, coding RTL, using industry standard design tools to translate RTL to gate-level netlist, run functional simulations and support SOC teams in enabling timing convergence.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills.

  • Solid verbal/written communication skills.

  • Effective team player with continuous learning mindset.

  • Willingness to balance multiple tasks.

  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience.


Master's Degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience in :

  • Logic design AND micro-architecture of complex IPs.

  • Solid RTL coding (Verilog ) and logic design background.

  • Experience with industry standard design tools and methodologies.

  • Excellent debugging skills.

Preferred Qualifications:

  • Experience in delivering complex IP designs.

  • Scripting and SW skills.

  • Willing to mentor junior design engineers.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-11 Expires: 2022-06-11

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AI/ML Logic Design Engineer

Santa Clara, CA 95050

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