21 days old

Analog/Mixed Signal Design Engineer/Lead

Intel
San Jose, CA 95113
  • Job Code
    JR0222057
Job Description

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, come join us to do something wonderful.

As an Analog Mixed Signal Design Engineer/Lead you will be part of a team designing various analog/mixed-signal circuit designs on Intel FPGAs such as Phase lock loops (PLLs), Delay locked loops (DLLs), and other clocking circuits, regulators and bandgaps, Analog to digital converter (ADC), IO circuits such as high voltage IO, RCOMP, etc. on advanced process nodes and have an opportunity to work on a diverse set of blocks and tasks in all phases of the design. One of the principal initial tasks of this candidate would be to own and design the full chip voltage regulator for the FPGA.

The ideal candidate will be an independent self-starter who can own/design an analog IP and deliver all aspects of the design and collateral, a motivated team-player who is willing to work with cross-functional and cross-geo teams to understand, articulate and solve problems, and an excellent communicator who is willing to represent the team in meetings and forums.

  • Technical path-finding, innovation and design of analog/mixed-signal circuits, particularly regulators and bandgaps to meet architectural requirements.

  • Bring your understanding of analog design trade-offs and design for process variation to design world class IPs.

  • Own specification documentation and circuit architecture for the block.

  • Design and deliver circuit schematics, perform pre layout and post layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, and RV checks for design reliability. Define and execute on design verification plans covering functionality, performance, and reliability meeting high volume productization requirement.

  • Work with custom layout team to define plan (floorplan, routing, matching, metal grid etc.) to meet circuit performance.

  • Collateral generation like Integration spec, BMOD, UPF, PERC, timing model, power model, RV, ICCT, IBIS, and alpha numbers.

  • Collaborate with logic designer, logic verification designer, structural physical design engineers, signal integrity, and power deliver engineer to define clear collateral handoff requirements to ensure quality IP integration.

  • Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification.

  • Conduct design reviews; actively contribute to design reviews in the team.

  • Represent the team on related IP in cross-functional meetings and co-ordination of deliverables.

In this role you will also bring:

  • Good communication and presentation skills to enable cross functional collaboration.

  • Effective prioritization and planning, time management skills.

  • Be willing to work in a dynamically changing, cross geo environment which requires ingenuity and skills to solve issues.

  • Team player - Be willing to work autonomously, and also collaboratively in a team environment.

  • Be a mentor; guide/train upcoming engineers.


Qualifications

Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

10+ years of relevant experience, experience should include:

  • Direct design experience with analog and mixed signal circuits (e.g. amplifiers, comparators, regulators, bandgaps, IO, PLL, etc.).

  • Experience with modern CMOS technologies.

  • Experience with analog simulation and reliability tools and flows.

  • Experience with planning for, defining, and analyzing post silicon characterization data; efficient silicon debug.

Preferred Qualifications

Experience in one or more of the following is considered a plus

  • MSEE or PhD in related field.

  • Experience/understanding of Verilog, static timing analysis, UPF, and related aspects of mixed signal design.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-04 Expires: 2022-06-04

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Analog/Mixed Signal Design Engineer/Lead

Intel
San Jose, CA 95113

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