13 days old

ASIC Logic Design Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0208444
Job Description

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.

An engineering position with Intel Foundry Services is a challenging but rewarding experience, allowing you to gain knowledge and experience in integrated circuit design and test, from chiplets to SoCs. As a member of our Silicon Solutions Engineering team, you will work alongside experienced engineers to solve new and interesting problems, making an important contribution to our exciting custom silicon IP and projects. The ASIC development position(s) for this listing is as follows: ASIC Design Engineer The ASIC team develops IP, SoCs, and chiplets to enable users and customers of Intel Foundry Services. Modern ASICs have grown exponentially more complex in order to enable greater functionality, to push the limits of performance and to use less power. Nevertheless, ASIC design engineering must absorb and adapt to this growth because high quality ASICs are crucial for success. Our team develops cutting edge high-performance, low-power techniques and methodologies which are then simulated and compared against the ASIC.


A design engineer owns one or more architectural functional blocks to perform all related tasks:

  • Perform logic design, Register Transfer Level (RTL) coding
  • Participate in the development of Microarchitecture specifications for the Logic components.
  • Provide IP integration support to SoC customers and represents RTL team.
  • Implement RTL in System Verilog, validating the design,
  • Synthesizing the design, static timing analysis and perform RTL to Netlist Equivalence Check
  • High-level Architecture through to the details of timing.
  • Perform analysis and trade-offs with modularity, scalability, DFX requirements, power, area, and performance.


Employees are encouraged to work remotely due to COVID-19; all new hire orientations will be done virtually. This is subject to change and employees deemed as essential workers may be required to work on-site. We are looking for enthusiastic individual with problem solving abilities, communication and desire to learn. Technically, a solid foundation of digital design (System Verilog) and object-oriented programming is desired but not required. Individual who is looking for a challenging and rewarding work experience should not hesitate to apply.


Qualifications

Minimum Qualifications:

  • Master's or Bachelor's degree in Electrical/Computer Engineering with 4 years of experience
  • Strong background in RTL Design
  • Working experience with logic design simulators (e.g. VCS/Verdi)
  • Debugging and problem solving skills

Preferred Qualifications:

  • SystemVerilog Assertions
  • Linux experience
  • Additional Programming Languages e.g., Python, Perl, C and C++, System C
  • Low Power Design using UPF
  • Synthesis and STA
  • Written and verbal communication skills
  • Project based teamwork

Inside this Business Group

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-04 Expires: 2022-06-04

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ASIC Logic Design Engineer

Intel
Folsom, CA 95630

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