Summary

Posted: Jul 23, 2020

Role Number:200182462

In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.

Key Qualific...Summary

Summary

Posted: Jul 23, 2020

Role Number:200182462

In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.

Key Qualifications

• The ideal candidate will have 5+ years of hands on experience in physical design and large chip integration.
• Needs to be familiar with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Must have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies.
• A detailed understanding of database management issues will be required.
• From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Education & Experience

MSEE or equivalent is required

Additional Requirements