10 days old

CAD Engineer/EDA Developer

Intel
San Jose, CA 95113
  • Job Code
    JR0211219
Job Description

The Custom Structured ASIC Engineering Group (eASIC) Team within Intel's Programmable Solutions Group (PSG) is looking for a Software Engineer.

In this position, responsibilities for this role include, but are not limited to the following:

  • Candidate develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems arising in Structured ASIC design.
  • Assessing architecture and hardware limitations, plans technical projects in the design and development of CAD software.
  • Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters.
  • Develops routines and utility programs.
  • Prepares design specifications, analysis and recommendations for presentation and approval.
  • May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.

Ideal candidate should have a deep experience in the Static Timing Analysis and/or logical synthesis areas.


Qualifications

Education Requirement:

  • Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6 years of industry work experience, or
  • Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of industry work experience, or
  • PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 2 years of related work experience.

Minimum Qualifications

  • 6 + years in C++ and scripting languages programming in CAD area.
  • Bachelor's degree or Master's degree in Mathematics, Computer Science or electrical engineering.
  • Bachelor's degree + 5 years of relevant experience or Master's degree + 3 years.


Preferred Qualifications and experience in at least one of areas:

  • Static Timing Analysis.
  • Timing optimization, placement and routing for ASIC and FPGA.
  • Logical synthesis.
  • Formal verification.
  • Open Access Data Base.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-17 Expires: 2022-06-17

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CAD Engineer/EDA Developer

Intel
San Jose, CA 95113

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