9 days old

CIT Logic Design

Folsom, CA 95630
  • Job Code
Job Description

This is an exciting time to be at Intel - come join our Chipsets Ingredients Team which is part of the Chipsets Silicon Group (CSG). Intel is transforming and so is CSG. Here at CSG we create products that empower people to live a better life.

We at CIT are looking for a highly motivated logic/RTL design engineer who will be responsible for the definition and implementation of clocking solution for client and server chipsets in cutting edge internal and external technology nodes. In this unique role the scope of learning opportunities, contributions and influence expands over on-die, multi-die and system level clocking solutions. As system level clocking protocols are the backbone of modern multi-die power management schemes, the role naturally expands into great exposure and contribution opportunities into low-power architecture and design. You will be responsible for the development of all new clocking IPs for the various market segments that CSG caters across Intel.       

Your responsibilities will include, but not be limited to one or more of the following aspects of the design flow which encompasses all aspects of logic design methodology

  • Feature feasibility study, performance analysis and micro architecture of latest feature requirement

  • Digital design of a wide variety of logic functions, with emphasis on multi-clock and multi-power domain designs

  • Register Transfer Level (RTL) HDL design feasibility, development and debug

  • Co-development of design test plan and validation strategy with validation team

  • Providing IP integration support to SoC customers

Behavioral traits we are looking for:

  • Technical leadership with good communication, interpersonal and problem solving skills

  • Motivated, self-directed and willing to work effectively both independently and as a team


Minimum Qualifications:

The candidate must possess a Bachelors in Electrical, Computer or any engineering related field and 3+ years of experience or Master's degree in Electrical, Computer or any engineering related field with 2+ years of experience in:

  • Microprocessors, computer system architecture VLSI design

  • Digital state machine architecture and logic design

  • RTL quality checks (Lintra, CDC, VCLP)

  • Simulation-based debug (VCS, Verdi, DVE)

  • Exposure to Static Timing Analysis, timing convergence and synthesis

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations
US, California, Santa Clara; US, Arizona, Phoenix;

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-08-08 Expires: 2022-09-08

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CIT Logic Design

Folsom, CA 95630

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