Do you want to engineer the future? Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us, and help create the next generation of technologies that will shape the future for decades to come. We are designing future generations of high-performance Intel E-Core CPUs using the most advanced and innovative process technologies. These CPUs help power the latest generation of Intel laptops and desktops, 5G base stations, micro-servers, Chromebooks for students and other Artificial Intelligence and Machine Learning devices.

We are seeking an SOC Design Engineer to work with a diverse team designing Intel's next generation products and are looking for someone who has passion around improving the way we solve complex problems through the work of the team as wells as their own direct contributions.

Your responsibilities in this highly visible role will include, but not be limited to:

• Develop, support and drive project execution backend signoff performance verification flows for cell-based and/or transistor-based designs.

• Drive solutions to perform sign-off verification using Engineering Design Automation (EDA) tools including 1 or more of Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction, ECO, or SPICE circuit simulation.

• Interface with Design Team to create or test flows/scripts to analyze design methodologies for cell-based and/or transistor-based designs

• Develop custom optimized solutions to address design requirements for leading-edge process technologies.

• Validate PDK technology, library files and other collaterals used for either standard cell or custom-transistor design, layout, and signoff with EDA CAD tools.

• Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies

• Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.

• Document and help with guidelines/specs

• The ideal candidate should exhibit the following behavioral traits

• Good inter-personal, clear communication and good teamwork skills

• A can-do attitude driven by research and thriving on challenges

• Self-motivator with strong problem solving skills

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

For information on Intel's immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications:

Candidate must have a Bachelors with 1+ years' experience in: - OR - a Master's degree in Electrical/Computer Engineering or related field and experience in:

• Physical Design and Verification Tools, Flows and Methods used in VLSI back-end standard cell based design.

• Coursework in VLSI, Digital and/or Analog Integrated Circuits

• Using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: STA, Power, ECO, SPICE circuit simulation, statistical variation analysis, noise, cross-talk, OCV and/or ERC flows

• Linux environments and basic shell scripting

• Programming in 1 or more scripting languages such as Python, Perl and/or Tcl

Preferred Qualifications:
1+ years of experience in 1 or more of the following:

• Backend design EDA tools from Synopsys, Cadence and/or Mentor Graphics

• In-house Intel tools for high-speed custom digital designs

• Standard-cell liberty format syntax or digital circuit device-level SPICE modelling

• Standard formats from 1 or more of gate-level netlist, standard parasitic formats and/or SDC constraints

• Knowledge of Cadence Design Tools: Virtuoso Schematic Editor, ADE

• EDA tool Tcl API coding

• Advanced programming data structures

• Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.