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Job CodeJR0192657
The world is transforming - and so is Intel! Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world.With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful!
As part of the IP Engineering Group, the Product Library team is looking for experience standard cell library design engineer in the area of design, development, automation and delivery of standard cell and register file using Intel latest process technology for use by Intel CPU, Atom, Graphics, mixed signal IPs, Client, Sever, Chipset projects and IFS Foundry customers.
The successful candidate will be part of the production library team responsible for standard cells circuit design and optimization, UDP (user defined primitive) verilog, behavioral verilog, mentor ATPG modeling and scan model delivery of standard cell collateral using leading process technology for use by Intel's product design teams and Foundry customers
.Responsibilities include, but are not limited to:
- Design and implementation of combinatorial and sequential circuits for Intel's newest process technologies, Circuit extraction and optimization for power/performance/robustness
- Silicon Smart/Primelib Synopsys tools to configure, generate Verilog and mentor models, validate functionality of std cells generating test benches and vector simulations.
- Development of automation for functional validation, quality checking, performance and reliability verification, enhancing flows for greater productivity and faster turn around time.
- Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
In addition to the qualifications listed below the ideal candidate will also have:
- Excellent analytical and problem-solving skills
- Strong verbal/written communication skills
- Effective team player with continuous learning mindset
- Willingness to balance multiple tasks
- Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process
Qualifications
Minimum
qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum
requirements and are considered a plus factor in identifying top
candidates.
Minimum Qualifications:
Candidate must have a Bachelor's degree with
4+ years of experiences in the field of electronics
engineering or hardware engineering, Electrical and/or Computer
Science/Engineering or related fields - OR - Master's
degree with 3+ years of experiences in the field of
electronics engineering or hardware engineering, Electrical and/or
Computer Science/Engineering or related fields
with:
- Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics.
- Excellent collaboration skills across geographically distributed teams and being able to handle ambiguity while developing expertise in new areas and delivering excellent, quantifiable results will be key to success in this role.
- Excellent organizations and coordination skills comprehend change in direction and gear team effectively towards changes.
- Excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner.
- Standard Cell Library design, extraction, characterization, validations experience in one or more areas of VLSI Design (ckt Design, Physical Design, Front End Design, Simulation, Timing Analysis, Reliability Analysis)
Preferred
Qualifications:
- Extensive experience with standard cell library content definitions, extraction, characterization, liberty models, device variation, Sil2Sim debug and analysis.
- Extensive experience working with EDA vendors to drive new features and capabilities
- Experience in the development of design automation tools/flows
- Strong knowledge of industry-standard EDA tools for VLSI circuit and layout design
- Good engineering acumen and analytical skills. Quick learner with debugging skills.
- Customer oriented and able to work in a dynamic environment
- Lead and mentor junior engineers
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Other
Locations
US, California, Santa
Clara;US, Oregon, Hillsboro;US, Texas,
Austin
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified
applicants will receive consideration for employment without regard
to race, color, religion, religious creed, sex, national origin,
ancestry, age, physical or mental disability, medical condition,
genetic information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance.
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