24 days old

CPU RTL Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

The world is transforming and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth. The Advanced Architecture Development Group (AADG) is a CPU Core development team and we believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. 

AADG's Load/Store Unit and L2 cache RTL team is looking for an experienced engineer with in-depth knowledge of CPU load-store unit design. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you to please join us, to do something wonderful!

As a senior member, your responsibilities include, but not limited to:

  • Development of architecture and microarchitecture specifications.

  • RTL implementation, delivery of high quality logic design that meets functional and PPA goals

  • process technology exploration to achieve the highest performance per watt on leading edge process technology

  • Work closely with verification team in determining the proper validation strategy for new design and defining and providing feedback on test plans

  • Drive design convergence, perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a manufacturing-ready design database


Minimum Bachelor's degree in Electrical/Computer Engineering, Computer Science or related Computing discipline and 8+ years of experience - OR - a Master's degree in Electrical/Computer Engineering, Computer Science or related Computing discipline and 6+ years of experience - OR - a PhD in Electrical/Computer Engineering, Computer Science or related Computing discipline and 4+ years of High performance CPU design experience:

  • Knowledge of coherency protocols, total store ordering, TLB, paging, and cache design are essential.

  • Knowledge of CPU architecture, including the concept of Instruction Fetch, Decode, Out of Order execution, Register Renaming, Branch prediction

  • Knowledge of Verilog or SystemVerilog

  • Understanding of high performance CPU design techniques

  • Understanding of power reduction techniques

  • Understanding of SoC Physical design flow from high level design to synthesis, place and route, timing and power optimization

  • Understanding of trade-off and optimization techniques between Performance, Power and Area

  • General scripting and programming skills (Python, Perl, C/C++, etc.)

Preferred Qualifications:

  • Familiarity with functional verification or formal verification is a plus

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-01 Expires: 2022-06-01

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CPU RTL Design Engineer

Hillsboro, OR 97123

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