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Job CodeJR0203230
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Jobs Rated187th
Intel's vision is to
continue to transform how the world processes information. Join an
inclusive team with one focus: the relentless pursuit of datacenter
architecture innovations to satisfy the needs of the next breed of
cloud, hyperscale, web 2.0 and enterprise applications and the
ever-growing data capacity and bandwidth demands. The solutions
developed by this team over the last decade have formed the
foundation of the modern datacenter processing architecture and led
to rapid growth of both the Intel's datacenter business and the
overall cloud and datacenter industry.
This datacenter
architecture team at Intel is seeking qualified candidates to
architect advanced RAS Reliability, Availability, Serviceability,
and Error Handling capabilities and solutions for datacenter
products and
SoCs.
Responsibilities:
- Define, document and communicate RAS and Error Handling architectural requirements to hardware IP components and SoC subsystems, and review implementations for correctness and completeness.
- Assess and identify error mitigations to address the needs of a wide range of market segments.
- Participate in new product development, comprehend customer technical requirements, develop architectural solutions to meet those requirements
- Author architectural specifications and other technical collateral
- Collaborate with design and verification teams to ensure implementation is in accordance with the specifications, while taking into account the Silicon technology trends, cost, schedule and performance tradeoffs.
Qualifications
Minimum Qualifications:
Bachelor's degree in Electrical, Electronic Engineering, Computer Engineering, Computer Science or related technical field and 4+ years relevant work experience; OR Master's degree Electrical, Electronic Engineering, Computer Engineering, Computer Science or related technical field and 2+ years relevant work experience; OR PhD in Electrical, Electronic Engineering, Computer Engineering, Computer Science or related technical field + 1+ years relevant work experience in:
- Datacenter/server main CPU hardware architecture, logic design and/or validation.
- Main processor RAS features, error handling, detection, containment and recovery.
- Primary experience must include RAS and error handling architecture and interaction with operating system software and datacenter platform firmware.
- Knowledge of modern architectural techniques regarding reliability of microprocessors.
Preferred Qualifications:
- 3+ years of experience in architecture/logic design and/or validation, including 1+ years of experience in main processor RAS features, error handling, detection, containment and recovery
- In-depth understanding of the interaction of machine check architecture and error flows with system firmware/software.
- Familiarity with cloud computing software paradigms
- Detailed knowledge of multiprocessor server system architecture, memory and input-output subsystems, high-speed interconnects, operating systems/hypervisors, platform firmware, Error correcting codes (ECC).
- Experience working in RTL development design environments.
- Knowledge of RTL design and languages, SoC design and integration, VLSI CMOS logic circuits and timing.
- Experience with the fundamentals of architecture work, including best practices for developing, evaluating and documenting hardware architecture features is highly valued.
- Experience successfully interacting with cross-disciplinary teams, tracking deliverables and milestones, with attention to detail.
- Experience in system debug in a datacenter environment.
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations. DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other
Locations
US, California,
Folsom;US, Oregon,
Hillsboro
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified
applicants will receive consideration for employment without regard
to race, color, religion, religious creed, sex, national origin,
ancestry, age, physical or mental disability, medical condition,
genetic information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance.
Jobs Rated Reports for Architect
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