14 days old

DDR PHY Logic Design Engineer

Folsom, CA 95630
  • Job Code
Job Description

The Mixed Signal IP Solutions Group (MIG) within the IP Engineering Group is looking for a Logic Design Engineer. You will work on high-speed digital design and is targeted towards low power optimized implementations of high speed IPs.

Responsibilities of the role include, although not limited to:

  • Implementing RTL in System Verilog, validating the design, synthesizing the design and closing timing.

  • You will also have an opportunity to work on high-level understanding of the architecture through to the details of timing.

  • You will contribute to specifications at multiple levels, including the HAS and MAS (microarchitecture spec).

  • Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills.

  • Solid verbal/written communication skills.

  • Effective team player with continuous learning mindset.

  • Willingness to balance multiple tasks.

  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process.

  • Willingness to work with cross-functional teams analytic and debugging skills.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's degree in Electrical/Computer Engineering with 4+ years of industry experience.


Master's degree in Electrical/Computer Engineering with 3+ years of industry experience with:

  • RTL development in System Verilog.

  • Microarchitectural spec development of new features/functionality, including trade-offs and documentation.

  • Low power design with multiple power domains.

Preferred Qualifications:
Experience in:

  • Simulation and debug, using VCS/Verdi/QuestaSim.

  • DDR/LPDDR technologies.

  • Synthesis and Speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-offs.

  • Analog design concerns and driving to an optimal solution between analog and digital designs.

  • Debugging mixed signal validation.

  • Post-silicon debug.

  • Development of schedules/timelines for design development.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.

Posted: 2022-06-15 Expires: 2022-07-17

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DDR PHY Logic Design Engineer

Folsom, CA 95630

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