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Job CodeJR0221924
IPG builds the silicon
and platform infrastructure for Intel's silicon design teams. IPG
is comprised of a reusable pool of infrastructure IP blocks, design
enabling services such as tools and automation, and a best-in-class
post silicon ecosystem that ramps quickly to high volume
manufacturing and validation. Our primary mission is to protect
Intel's brand by providing the infrastructure necessary to enable
all of Intel's products to hit the market on a dependable and
predictable cadence.
This person will be
responsible for support and development of a GDS and netlist tiling
platform supporting Intel developed memory compilers on
Linux.
Responsibilities would
include:
Customer support.
Code development and maintenance.
Working in a small team environment.
What we offer:
We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work!
We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.
Qualifications
Minimum
qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum
requirements and are considered a plus factor in identifying top
candidates.
Minimum
Qualifications:
Must have a BS, MS or PhD in Electrical Engineering or Computer Engineering or Software Engineering.
Must be very familiar with SRAM, RF, and ROM memory design and layout flows.
Competent in object oriented C++ with experience in its debugging and build flows.
Expert in TCL and its use in an embedded environment.
Practical experience coding from a specification.
At least 5 years of product develop and support in an industrial environment.
Practical experience in software quality assurance.
Experience with configuration management and advocating best practices.
Experience in GDS, LEF, and netlist file formats.
Experience with OAS file format is desired.
Experience with SWIG and BOOST is desired.
Experience with Python is desired.
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Other
Locations
US, Oregon,
Hillsboro
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified
applicants will receive consideration for employment without regard
to race, color, religion, religious creed, sex, national origin,
ancestry, age, physical or mental disability, medical condition,
genetic information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or
ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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