The person will be responsible for Design Automation needs using industry CAD tools and inhouse CAD tools for memory designers for compiler development, characterization, PV and LV verification, and regressions in a fast-paced environment. The successful candidate must possess solid analytical skills, programming skills, self-driven, teamwork and detail-oriented, worked on EDA tools for PV or LV flows.

Responsibilities include:

• Using your hands-on skills to improve design environment and design efficiency in any or some of PV flows such as static timing, noise analysis, extraction, simulation, and reliability verification.

• Defining, investigating, and providing solution/approaches of technical EDA challenges. It involves problem analysis and requirements definition, followed by implementation, test, deployment, and technical support to enable better utilization of CAD tools.

• Collaborating with design teams on methodology development and interact closely with design teams to mature the CAD solutions for production use.

• Owning processes related to design, layout, deployment of productivity-enhancement tools, methodologies.

• Providing training, documentation, and other collaboration sessions to the design teams as necessary to learn new flows and improve design efficiency.

• Memory characterization for timing, power, and noise.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• The candidate must possess a Bachelor's degree ( with 7+ years industry experience in CAD and Chip design) or Master's degree in Electrical Engineering , Computer Science or Computer Engineering with 5+ years of total experience in CAD or VLSI.

2+ years of experience in below areas:

• Shell scripting and scripting programming languages (Perl/Python/Ruby/TCl/Skill) in Linux-based environments is required in at least two or more of these.

• Software development flows and architecture.

• Digital circuit and layout design or support to CAD tools.

• EDA tools such as StarRC, ICV, NanoTime, ICV, Finesim.

• Solid experience in extraction flows for custom designs.

Preferred Qualifications:

• Understanding of custom layout tools (Virtuoso) is a plus.

• Understanding of custom schematic tools (Virtuoso) and simulation (finesim, Hspice) is a plus.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

India, Bangalore;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.