3 days old

Design Automation Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0228392
Job Description

Do you want to create world changing technology that improves the life of every person on the planet? Want to help drive innovation, shape the future of all humankind using Silicon and Software? As part of our Design Engineering organization, you will do just that. Join us and you will help ensure we save Coral Reefs using Artificial Intelligence, enable Desktops to sip energy while idling, deliver the fastest processors, and much much more. Our core values are, fearless Innovation, Results Driven, Inclusion, Quality, and Integrity are an integral part of our Intel DNA.

About the team:

This position for a RD Engineer/Automation Engineer in the Design Enablement (DE) organization. You will develop world class software that models cutting edge technology design rules, optimizes PDK development, and helps deliver complete, accurate PDKs to our customers on time. You will collaborate closely with our advanced process Technology Definition team, EDA vendors and PDK developers to optimize Intel's PDK competitiveness using both traditional automation and Machine Learning (ML) algorithms. You will lead and project manage tasks related to advanced technology node PDK roadmaps, schedules, and other deliverables.

About the role:

  • Develops software solutions related to PDK development and QA using python, ruby, C++
  • Writes automation to build, automatically create highly permuted layout testcases, designs to assess process technology competitiveness.
  • Develops flows/scripts to analyze and test design methodologies, identify opportunities for more efficient PDK deliveries.
  • Collaborates with, and evaluates EDA vendor products to augment Intel's PDK development, testing methodologies
  • Communicates technical projects, scope and schedules to senior management with-in and outside of DE organization.


Qualifications

Minimum requirements:

BS in EE/CS/CE, MS preferred with with 6+ years of industry professional experience in the following areas:

  • Prior knowledge and experience of CAD/EDA tool development.
  • Experience with any of the following: Custom layout experience, Automated PnR, within a Design Automation role involving backend EDA tools (layout editors, tech files, Pcells, auto-routing, macros, environment, etc.) and design rule familiarity on advanced process nodes.
  • At least two of the following areas required: C++, Python, Ruby, or Tcl
  • Debug and problem solving skills required

Preferred:

  • Development and support of build processes using a continuous integration system and/or Makefile-type of build flow

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Arizona, Phoenix;US, California, San Jose;US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-08-14 Expires: 2022-09-14

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Design Automation Engineer

Intel
Folsom, CA 95630

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