In this position, you with be part of the Xeon Engineering Group (XEG) Test Technology management team, responsible for managing the engineering team to execute SCAN integration and ATPG, achieve high test coverage, and drive test coverage analysis and test coverage improvements at the Chip-Top level for the SoCs that comprise the XEG silicon product portfolio.

Responsibilities:

Hiring and training and development of engineers in SCAN, ATPG, and other standard DFT techniques; career development and performance management of engineering team.

Resource management; assignment of engineers to meet the staffing requirements of the various SoC'so Manage the day-to-day tasks of the engineering team in the following areas:

• Collaboration with the physical design team to ensure correctness of SCAN implementation for SoC partitions.

• Evaluate design readiness for scan insertion through RTL Scan DRC tools.

• Running and evaluating SCAN insertion through synthesis tools and refining scan insertion recipe for maximum test coverage.

• Running ATPG analysis to ensure quality scan chain construction and meeting basic coverage goals.-

• Debug and resolve violations flagged by post-construction scan design rule checking tools to ensure correct construction.-

• Deliver validated ATPG content to manufacturing team for silicon test; collaborate with manufacturing team during silicon bring up.

• Establish execution plans and schedules; track technical metrics/indicators and execution progress to plan; report out to XEG management and SoC design team management; simultaneously drive multiple SoC products.

• Work with central tool and flow methodology teams to specify requirements needed by XEG designs and drive continuous improvement of these methodologies.

Qualifications

Minimum qualifications:

Bachelors degree or higher with 5 + years experience

DFT Engineer or Engineering Manager with 5+ years of experience

Preferred qualification:

• DFT Engineer or DFT Engineering Manager with 5+ year experience

• RTL experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT.

• Experience with ATPG tools, preferably Mentor TestKompress.

• SpyGlass DFT experience in setup and debug of violations.

• SCAN DRC rule checking experience.

• Ideal candidate is a self-starter, can organize complex issues and drive them to closure.

• Candidate can multitask and prioritize.

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, Massachusetts, Hudson

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.