10 days old

Design-for-Test (DFT) Implementation Engineer DFT Solutions Team

Intel
Allentown, PA 18101
  • Job Code
    JR0218853
Job Description

The Design-for-Test (DFT) Implementation Engineers of the DFT Solutions Team develop and deploy state-of-the-art DFT architectures, strategies, and flows and in turn use these creations to execute the DFT Implementation for current and next generation 5G Mobile Base-Station products.

You will be working with both external tier-1 customers and internal product design teams during their silicon design cycle as they develop System-on-a-Chip (SoC) solutions utilizing cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high-speed memory interface IP.

As a member of the Xeon and Networking Engineering Group (XNE) DFT Solutions Team, you are responsible for the holistic DFT Solution for a System-on-a-Chip (SoC) design and the below listed:

  • Development of the SoC Test Implementation plan to individualize the standardized DFT solutions to the SoC, including the hierarchical test architecture and the strategies to address SoC-specific DFT requirements

  • Definition of the standardized DFT flow steps, deployment of the tool infrastructure and flow automation to implement the SoC DFT in a highly repeatable and predictable fashion

  • Insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for High-Volume Manufacturing (HVM) testing of the design

  • Development of the Static Timing Analysis (STA) constraints for physical construction and timing closure in all DFT modes, and collaboration with the Physical Design team to achieve timing closure for the DFT modes

  • Collaborating with the HVM Test Engineering team during silicon bring-up and New Product Introduction (NPI).

  • Scaling the standardized DFT solutions to the wider XNE DFT Team across the products of the XNE portfolio


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:


Candidate must possess a BS in Electrical or Computer Engineering & 6+ yrs. exp. OR MS in Electrical or Computer Engineering & 4+ yrs. experience in:

  • SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, IEEE1149 JTAG Boundary SCAN, IEEE1687 IJTAG

  • DFT architecture development and planning for an SoC

  • Test insertion, test pattern generation, simulation, and validation

  • Industry-standard DFT tools such as Siemens Tessent DFT, Synopsys DFT Compiler, DFTMax, TetraMax

  • Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug

  • Programming skills; experience writing routines for data manipulation using advanced data structures; languages include PERL, Tcl/Tk


Preferred Qualifications:

  • Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience

  • Experience with the DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-09 Expires: 2022-06-09

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Design-for-Test (DFT) Implementation Engineer DFT Solutions Team

Intel
Allentown, PA 18101

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