18 days old

Design verification engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0216729
Job Description
Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Bachelor's degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science CS and 3+ years of relevant work experience OR a Master's degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science CS and an additional 2+ years of relevant work experience with:System VerilogDeveloping scalable and portable test-benchesVerification methodologies and tools such as simulators or waveform viewers or build/run automation or coverage collection or gate level simulationsPreferred Qualifications:Experience with DDR

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Folsom


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-08 Expires: 2022-07-10

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Design verification engineer

Intel
Santa Clara, CA 95050

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