19 days old

DFT Engineer Staff Lead

Santa Clara, CA 95050
  • Job Code
Job Description

As an integral part of Intel's IDM 2.0 strategy, the Corporate Planning Group (CPG) is established matrix reporting to CEO, to drive world class operational execution and superb centralized planning to address our customers' needs. CPG will accelerate the success of IDM 2.0 and enable business priorities across internal manufacturing, external manufacturing, and support all our customers for growth and success. CPG maximize impact with cross BU, TD, and Manufacturing alignment, display independence for our external wafer sourcing and IFS customers and bring us closer together as One Intel.

This position will be part of the CPG Foundry Technology and Engineering (FTE) team chartered with accelerating product leadership through strong collaboration and execution with our 3rd party Foundry, Assembly and Test suppliers. FTE manages Foundry and OSAT to deliver compelling, timely, Intel-aligned technology and enable Intel to leverage it most effectively, leadership product design and manufacturing.

FTE seeks a dynamic Design For Test staff member to lead a team of DFT engineers responsible for, but not limited to:

Defining design-for-test methods for products that are manufactured in external foundries.
Partners with the manufacturing teams and the foundries to define and drive implementation of DFT structures for logic, memory, high-speed I/Os, analog circuits that maximize benefits from external process nodes for production test time reduction, yield improvement, and reduced outgoing product quality.
Works with EDA vendors to define enhancements to test CAD tools.
Engages with external design services companies to implement design-for-test features as needed.
Design and verify DFT structures when needed.
Create, simulate and verify Scan ATPG patterns as needed.
Create functional tests and corresponding test patterns as needed. Support silicon brings up test patterns.
Performs diagnosis of test patterns on silicon.
Participate/drive failure analysis in silicon production


You must possess the below minimum qualifications to be initially considered for this position. This Position is not eligible for Intel immigration sponsorship

Minimum Qualifications:

The candidate must possess a Bachelor's Degree in Electrical engineering or related field of study with 6+ years of experience DFT on products that went into production

or Master's degree with 4+ years of experience in DFT on products that went into production.

6+ years of relevant experience writing scripts and small software programs for automation, using RTL and physical design tools, EDA vendor tools such as scan ATPG, memory BIST, industry DFT practices in HSIO test, PLL test, and debug methods and production test equipment.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, San Jose

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-05 Expires: 2022-06-05

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DFT Engineer Staff Lead

Santa Clara, CA 95050

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