Were looking for an EDA Tools Software Engineer to be part of our Design Rule Optimization (DRO) team of the Process Design Kit (PDK) group, within the Design Enablement (DE) organization.

The primary function of the DRO team is to further develop and deploy the Ptech tool which stores design rule data (DR) in a machine-readable database, used for PDK automation to automatically generate DR-compliant technology files and layout test structures.

The DRO team works closely in partnership with Intel's technology development, EDA suppliers, PDK functional areas, Design Rule Definition, and OPC teams to optimize Intel's process technology competitiveness using traditional automation and Machine Learning (ML) techniques from highly permuted layout test case structure generation.

Youll be responsible for but not limited to the following activities:

• Continuous building of Ptech database in CI/CD to represent Intel's most advanced process technologies

• Making software improvements to support new concepts, and improve efficiency and robustness

Important behavior traits we look for:

• History with respect to quality

• Customer orientation

• Problem-solving skills

This is an entry level position and compensation will be given accordingly

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Education level:

• Bachelor of Science degree in Electrical Engineering, Computer Science, or Computer Engineering with 1+ year of experience

Or

• Master of Science degree in Electrical Engineering, Computer Science, or Computer Engineering

Experience with the following:

• At least one of these programming languages such as C++, Python, Ruby, Perl, Tcl

• Linux

• Custom or ASIC layout design

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, California, San Jose

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.