About the job

The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

Responsibilities include:

• Develop physical layout verification design rule checker (DRC), Layout vs Schematic (LVS), and RC extraction runsets using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)Work with the process development teams at Intel to define specifications for DRC, LVS, and RC extraction runsets
• Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders
• Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runsets
• Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification
• Assess architecture and hardware limitations, plans technical projects in the design and development of CAD software
• Help library teams at Intel with technology path finding activities

Important behavior traits we look for:

• Creative, independent, and out of the box thinker with strong problem-solving skills and analytical ability
• Drive innovation and initiatives to enhance existing automation, tools, and methodology
• Identify and analyze problems, plans, tasks, and solutions
• Cultivate and reinforce appropriate group values, norms, and behaviors
• Perform in a dynamic and challenging environment with drive and creativity

About our organization

This position is within the Design Enablement (DE) organization of Technology Development. The Runset Development team within this organization is looking for talented individuals to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

MS/Ph.D. in Electrical Engineering, Physics, or related field with 6+ month of academic work in the following areas:

• Unix/Linux operating system
• With at least one of the following: C++, Python, Perl, TCL
• Knowledge of DRC/LVS runsets and EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)
• Familiarity with VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures

Preferred Qualifications:

• Experience with working in software repository management tools like Git
• Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.