17 days old

Electrical Low Yield Analysis Pathfinding Engineer

Intel
Phoenix, AZ 85003
  • Job Code
    JR0222670
Job Description

Microelectronic Packaging Engineers provide project management, package design/development and sustaining support for integrated circuit or semiconductor assemblies, various other electronic components and/or completed units.

Responsible for the thermal/mechanical/electrical design, analysis, and development of electronic packages.

Defines overall package performance and specification and realizes technology certification through layout design and test vehicle design. Conducts tests and research on basic materials and properties. Establishes material specifications for contract assemblers and raw material vendors and interfaces with Quality Assurance and Purchasing regarding material quality and vendor performance.

Provides consultation concerning packaging problems and improvements in the packaging process.

Responds to customer/client requests or events as they occur.

Develops solutions to problems utilizing formal education and judgment.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. 

Minimum Qualifications:

  • Must possess a Masters Degree with 4+ years of experience or PhD with 2+ years of experience in Physics, Electrical Engineering, Materials Science or other relevant applied Engineering Degree.

Preferred Qualifications:

  • Experience with product design and debug and DFx methodology.
  • Experience with device physics and common Si fail modes and mechanisms.
  • Experience with Si Test Program development and evaluations - especially parametric tests.
  • Experience with Electrical Fault Isolation of parametric structures.
  • Detailed knowledge in some or all of the following package-level fault isolation techniques: Curve Tracing, Electrical Hand-probing, EBIC, IBIC, TIVA, LIVA, TDR, EOTPR, SQUID, SSM, ELITE.
  • Familiarity with fab wafer processing, especially back-end processing.
  • Experience with test experience and test Program development knowledge.
  • Prior knowledge to incorporate optical devices into scope.
  • Knowledge of sample preparation such as: mechanical cross-sectioning, planar grinding, de-lidding, and FIB.
  • Knowledge of the de-bug circuit modification process such as FIB drilling, metal deposition, enhanced etch also a plus.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-17 Expires: 2022-07-18

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Electrical Low Yield Analysis Pathfinding Engineer

Intel
Phoenix, AZ 85003

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