24 days old

Experienced Validation Design Automation Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0208108
Job Description

As part of an innovative and transformative next generation X86 CPU product development team, you will drive TFM enabling efforts for RTL and Design Validation (DV) needs. 

  • Responsibilities will include enabling the design environment, infrastructure, data managements solutions, EDA tools, and flows along with creating new methods for design automation towards best in class model simulation, validation, and continuous integration flows. 
  • Machine Learning techniques and Compute efficiency methods will be used to improve overall turn around time and ease of use for the RTL and Validation engineers. 
  • You will also be responsible for testing, deploying, and supporting production worthy flows to the team.
  • This requires expertise in industry standard EDA and internal PESG technologies including code generator tools for registers, interfaces, and DFx; simulation tools such as VCS; static lint/LP/CDC/DFx flows; wavetrace tools, UVM, Saola, Granite, and Triage. 
  • Expertise with scripting (Perl/Python) is a must. 


Qualifications

Minimum Qualifications:

  • Bachelor of Science degree in Electrical Engineering or Computer Engineering with 8 years of experience in IC Design, ASIC or Computer Aided Design (CAD). Or a Master of Science with 6 years of experience.

  • Experience with latest industry tools from either Cadence, Synopsys or Mentor.

  • Expertise in verification methodologies and tools such as UVM, design exercise and unit testing solutions, formal verification tools, emulation, FPGA, and regression collection, bucketing, and coverage metric solutions

  • High level understanding of industry standard EDA and internal CAD technologies including code generator tools for registers, interfaces, and DFx; simulation tools such as VCS and Xcelium; static tools for lint, low power (LP), cross domain clocking checks (CDC), and DFx flows.

  • Excellent programming skills: Unix, Perl, Python, Tcl or other

  • Practical experience with data management software is expected Git, Perforce, etc.


Preferred skills:

  • Demonstrate experience to interface with engineers, senior managers and stakeholders

  • Demonstrate experience to mentor, coach and lead small groups of junior engineers working across Intel sites

  • Excellent communication skills

Inside this Business Group

The Advanced Architecture Development Group (AADG) is a CPU Core development team in Portland, Oregon.  If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, please join us.  We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible.  Join us to do something wonderful!


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-04-26 Expires: 2022-05-27

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Experienced Validation Design Automation Engineer

Intel
Hillsboro, OR 97123

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