19 days old


San Jose, CA 95113
  • Job Code
Job Description

As a FPGA IP Design Engineer within the Design Creation and Debug group, you will be part of the Nios Embedded Design team developing Intel's next generation RISC-V based embedded processor cores targeting FPGA applications. The goal of this team is to make implementing powerful embedded hardware systems a straightforward and enjoyable task from design creation through debugging and performance optimization. The team is responsible in providing processor solutions targeting a wide of range embedded applications, and the full stack of embedded tools, GUI, model, OS specific device drivers.

Within the Design and Creation group, we have the fortune of interacting in the highly dynamic spaces in between programmable hardware and embedded software; designing tools and infrastructure to empower design engineers in both realms. Our work is varied and ranges from user experience, software architecture, hardware architecture, modeling, cross-language interaction, drivers and even RTOS enablement with plenty of opportunity to play anywhere in-between. We've assembled an energetic team of quality people and are looking for a couple more experienced candidates to help with the effort.

As a FPGA IP Design Engineer in this position, you will need to be an excellent digital logic designer with a mastery in System Verilog/Verilog, high speed timing analysis and closure, and familiarity in FPGA system design and methodology.

You will have a direct influence on our customers and the adoption of our products with tasks including the following:

  • Delivering RISC-V architectural processor designs and FPGA specific optimizations.

  • Collaboration with developers across hardware, software, and verification to ensure we develop design flows meeting our customers' needs.

  • Guide hardware release content, and serve as a liaison with the support, field, marketing, and product planning organizations.

  • Research, define, and validate key customer use cases, design flows, and application requirements.

  • Use Intel FPGA design tools and products like our customers to identify usability and productivity problems or missing features.

  • Utilize the Platform Designer system design tool and accompanying software toolchain for Intel's Nios soft processor and ARM-based SoC solutions.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • BS degree in Electrical/Computer/Software Engineering or equivalent and 6+ years of relevant industry experience

  • 6 years of experience in digital logic designs and integration, timing analysis and closure

Preferred Qualifications:

  • Solid understanding of RTL design and flows

  • Proficient in RTL design using Verilog/System Verilog

  • Experience with FPGA system design and methodology

  • Knowledgeable in designing RTL logic for FPGA architectures

  • Familiarity with embedded system integration

  • Familiarity with Quartus design tools

  • Experienced with RTL simulation

  • Familiar with C/C++ and/or Assembly programming

  • Familiar with Tcl, Perl, and/or Python scripting

  • Familiar with RISC-V, Nios V, embedded processor, embedded processor development, processor development

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-01 Expires: 2022-06-01

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San Jose, CA 95113

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