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Job CodeJR0208435
In this role responsibilities include although not limited to:
Develops and tests Engineering Design Automation tools
Creates flows and scripts to analyze and test design methodologies for RTL tools
Evaluates vendor practical capabilities to provide required products or services. You will work closely with EDA vendor representatives to drive improvements and new methodologies
Responsible for designing deploying and testing efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development
Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality
Responsibilities may be quite diverse of a nonexempt technical nature
U.S. experience and education requirements will vary significantly depending on the unique needs of the job.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.
Minimum
Qualifications:
The candidate must
be pursuing a Bachelors degree in Electrical Engineering, Computer
Science, Computer Engineering or related field with 3+
years experience -OR- a Masters degree in
Electrical Engineering, Computer Science, Computer Engineering or
related field -OR- PhD in Electrical
Engineering, Computer Science, Computer Engineering or related
field and have 3+ months experience in the
following:
Scripting: Perl/TCL/Python
RTL, Verilog, System Verilog
Software validation, regression
Unix/Linux environment
Preferred Qualifications:
Experience in:
Synopsys/Cadence/Siemens design tools
RTL/Logic design CAD tool
Logic Design, RTL Simulation, RTL Static Checks, Clock Domain Crossing, Low Power Design, UPF
Developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) for Intel products across multiple design sites
Basic ASIC design flows
Spyglass/Questa
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations. DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified applicants will
receive consideration for employment without regard to race, color,
religion, religious creed, sex, national origin, ancestry, age,
physical or mental disability, medical condition, genetic
information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance.
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