19 days old

Full Chip Power Lead Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0213399
Job Description

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person globally, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenges that come with changing the world.

The Programmable Solutions Group at Intel was formed through the acquisition of Altera, a leader in programmable logic.  We enable rapid time-to-market solutions for our customers across a wide array of industries, powering solutions in automotive, test and measurement, wireless and wireline communications, and datacenter infrastructure processing units (IPUs) to name a few.  Building on our industry leading Agilex FPGAs we are creating the future, leveraging leading edge process technologies as well as multi-chip module packaging capabilities for true heterogenous integration.

 

As Full Chip Power Engineer, you will be responsible for overseeing all aspects of FPGA and tile power optimization from device concept to production. In this highly-visible role, you will partner with multiple groups across the engineering organization and across the Business Units within the Programmable Solutions Group (PSG) to drive the development of PSGs power-optimized FPGAs and tiles.

 

This role will directly impact process selection and binning strategies, device and multi-chip package (MCP) architecture, silicon implementation methodologies and execution, and post-silicon correlation. The Full Chip Power Engineer is expected to have strong silicon design fundamentals and deep expertise in design closure methodologies for both custom and ASIC design implementations.

 

As the subject matter expert, you will provide support:

  • Oversee power from design concept to tape-in and production release.

  • Pre-silicon power optimization, at architecture and implementation levels.

  • Create plans for power optimization for both front-end and back-end stages.

  • Ensuring realized implementation aligns with the pre-silicon expectations.

  • Identify areas of improvement as needed throughout the design process.

  • Drive post-silicon learnings to improve methodologies for subsequent products.

  • Provide excellent communication, teamwork, negotiation and analytical skills.


Qualifications

Education Requirement

  • Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6 years of industry work experience, or

  • Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of industry work experience, or

  • PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 2 years of related work experience.

Minimum Qualifications

  • 6 plus years of experience with standard design tools and methodologies (Prime Time, Design Compiler, ICC, PnR, Timing, Power)

  • 6 plus years of experience with power analysis and optimization, including clock-gating, power-gating

  • 6 plus years of experience in program and script using Perl, TCL, Python

 Preferred Qualifications

  • 10 plus years of relevant industry experience

  • 6 plus years of experience with SoC projects at advanced process nodes (32nm and below)

  • Expertise in System and SoC power architecture

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-05 Expires: 2022-06-05

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Full Chip Power Lead Engineer

Intel
San Jose, CA 95113

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