21 days old

IFS Component Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0206317
Job Description

About the Group:
As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and a major provider of the US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can choose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry-standard design packages.

About the Role:
Component Design Engineer will be responsible for, but not limited to:

  • Create standard cell layout variants using specified rule set while optimizing the same for area, power and performance
  • Evaluate standard cell library content for different IFS node offerings, and competitive positioning of the same
  • Incorporate industry-standard tooling to successfully navigate trade-offs between power, performance, area, and cost at the system and chipset level
  • Create tool scripts and/or standalone scripts as needed to automate tasks, collect stats
  • The ideal candidate should exhibit the following behavioral traits:
  • Service mindset with a focus on solution velocity thrives in solving complex and cross-functional problems.
  • Analytical and problem-solving skills working with cross functional teams


Qualifications

You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must possess at least one of the 2 following degrees, plus the years of experience determined for each degree in the areas of expertise specified below:

  • Master's degree in Electrical Engineering, Computer Engineering or related field with 2+ years of related experience
  • Bachelor's degree in Electrical Engineering, Computer Engineering or related field with 3+ years of related experience

Required experience should be across the Standard Cell Library Generation process including:

  • Cadence Virtuoso and/or Synopsys Custom Compiler
  • Circuit simulation tools such as Synopsys Hspice and/or Cadence Spectre
  • Layout and schematic netlist generation, running layout-vs-schematic checkers and fixing issues found
  • Running layout verification tools/scripts and fixing layouts
  • Layout extraction using Synopsys StarRC and/or Cadence QRC
  • Cell characterization using Synopsys SiliconSmart and/or Cadence Liberate

Preferred Qualifications:

  • Experience with process layout rule decks and familiarity with technology file syntax and formats for Synopsys and/or Cadence tools
  • Writing Cadence Skill and/or Custom Compiler Tcl scripts, shell scripts for data collection, design checks etc
  • Understanding of common circuit types and layout implementations of the same, especially for advanced finfet nodes
  • Logic/memory process technologies such as planar, FinFET, GAA, CFET

Inside this Business Group

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-04 Expires: 2022-06-04

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IFS Component Design Engineer

Intel
Santa Clara, CA 95050

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