14 days old

IO Validation Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0217744
Job Description

In the Intel Validation Engineering group, Analog Validation, we take pride in validation of the best-in-class SOCs, Cores, and IPs that power Intel's products. We are involved from development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. As a member of the Intel Validation Engineering Group you'll play an active role in validation and debug to ensure our products meet the highest quality standards before they reach our customer's hands.

  • Develops and documents analog electrical validation requirements and tests for verification of Si designs

  • Investigates and resolves complex issues with hardware/BIOS/Firmware/Operating System

  • Implementations and recommends solutions.

  • Uses analysis to resolve electronic issues

The responsibilities include but not limited to:

  • Perform comprehensive System level margining and industry standard signal integrity spec validation for the I/O's of next generation of Data Center CPU.

  • Perform system margin measurement and validation of the high speed I/O's, PCIe Gen5 and UPI on next generation CPU's for data center

  • Perform Signal Integrity analysis and measurements of the I/O's, example I2C, SPI, PCIe, UPI and more

  • Systematically debug System level failures of the IO interface and independently resolve platform issues by working with board teams and external vendors

  • Tune and optimize the analog performance of the IO interfaces and create a UPM prediction model for HSIO interfaces based on validation results.

  • Develop DOE's and write test cases to exercise worst case data transaction scenario between transmitter and receiver of PCIe Gen5 to stress power delivery conditions.

  • Updates test plans and test cases based on inputs from the product specifications by working with OEM/ODM partners.

  • Works with hardware designers to determine test requirements and writes test cases, test plans and develops test tools for test projects.

  • Develops risk management plans based on all information available to determine technical and logistical risk to completing test activities as planned.

  • Hands on conduct test and/or manages daily execution of test plan including guidance of technicians internally and/or third- party test facility.

  • Reports test execution progress and issues to the engineering team, be willing to do basic issue triage and manages the issues from creation to closure.

  • Develop and test methodologies as needed for evaluating additional features and needs based upon lessons learned.

  • Use analog and digital pre-silicon simulation tools to verify analog/digital models, validation content and functionality of DFX implementations


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's Degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience -OR- a Master's Degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience in:

  • Signal measurement and validation for I/O's, example low speed I2C, SPI and high speed PCI Express, USB, SATA, Ethernet, etc.

  • Lab HW equipment and platform requirements for testing signal integrity of the high speed serial IO ports

  • Signal integrity (SI/PI) and SI simulation theory

  • High-speed (example: PCIe Gen5) and low speed (example: I2C) signal measurement methodology and equipment/utility/fixtures

  • Measurement equipment for data rates up to 32GBps for receiver and/or transmitter characterizations

  • Programming using Python and preferably one or two more software languages (C, C++, Verilog, System Verilog)

  • SerDes designs, tuning of serial I/O's and margining of serial I/O's

Preferred Qualifications

  • ASIC design, SerDes design and RTL designs is a plus

  • Low-power circuit design, DC/DC converters, I2C, SPI, power management methods, and analog design a plus

Inside this Business Group

The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-11 Expires: 2022-06-11

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IO Validation Engineer

Intel
Santa Clara, CA 95050

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