30 days old

IP Logic Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

Intel is seeking highly qualified engineers to join the CAG (Custom-Logic ASIC Engineering Group) within DCAI (Data Center and Artificial Intelligence Group) in our IP Platform Development team. We're looking for motivated, passionate, and talented design engineers to develop Accelerator platform IP blocks for our next generation HW accelerators. We're a strong, vibrant, cross site team that helps drive IP product development for Cloud and Data Center applications.

In this role, as part of the IP Platform Development team, you will need to be passionate about developing high-performance IP for HW acceleration of key Cloud and Data Center workloads. You will have an excellent opportunity to define and design the next generation Intel IP Platform for HW acceleration.

Responsibilities will include, but are not limited to:

  • Define and write architecture/microarchitecture specifications.

  • Design RTL logic using System Verilog including assertions/cover points, work with validators for design verification, synthesize the design and close timing.

  • Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.

  • Work with both internal and external high-performance interface IP's such as PCI-Express, AXI, IOSF.

  • Work closely with Physical Design Engineers for floor planning activity, synthesis, and timing analysis.

  • Participate in design and code-reviews with other design engineers.

The ideal candidate will have the following skills in addition to the qualifications listed below:

  • Must be a team player with the experience to interact effectively on a technical level with others.

  • Strong problem-solving skills.

  • Effective verbal and written communication skills.

In this position you will gain valuable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


  • Bachelor's degree in Computer / Electrical Engineering or related field and 3+ years of industry work experience or

  • Master's degree in Computer / Electrical Engineering or related field and 2+ years of industry work experience or

  • PhD in Computer / Electrical Engineering or related field and 1+ years of industry work experience.

Minimum Qualifications:

  • 3+ years of experience in RTL design including functional and performance validation using System Verilog as well as logic synthesis and timing closure.

  • 2+ years of experience in IP integration and debug.

  • 1+ years of experience in Formal Property Verification (FPV) as well as scripting languages such as Python/ Perl.

Preferred Qualifications:

  • 1+ years of experience in bus architectures such as AMBA AXI/APB protocol, IOSF, PCI-Express.

  • 1+ years of experience in IP / SOC physical design and database convergence.

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-04-27 Expires: 2022-05-28

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

IP Logic Design Engineer

San Jose, CA 95113

Join us to start saving your Favorite Jobs!

Sign In Create Account
Powered ByCareerCast