22 days old

IP Logic Validation Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0219299
Job Description

Intel's IP Engineering Group (IPG) is currently looking for the candidates to deliver best in class solutions for our customers. This position will work on state of the art analog mixed-signal IP designs which will be integrated in Intel's flagship client/server/graphics SOCs.

In this position you will be part of a world-class Silicon design organization working with a team of highly talented engineers working on cutting-edge IP/SoC architectures, advanced Silicon design and process technologies, with tremendously exciting opportunities for industry-leading engineering innovations.

What we offer:  

  • We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.  

  • As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.  

  • We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).  

  • We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work!  

  • We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today. 


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

  • Masters with 5 years of pre-Si Validation experience

  • PhD with 0 years of experience


Preferred Qualifications:

  • Relevant ASIC design/validation experience in front end processes including RTL functional, performance and power verification.

  • Expertise in digital logic design, chip architecture and microarchitecture.

  • Solid leadership skills and has the willingness to work independently.

  • Expertise in verification of design blocks (IP) for system-on-chip (SoC) components.

  • Expertise in System Verilog and OVM or UVM based verification methodologies.

  • Experience in OOP concepts, coverage based random validation.

  • Knowledge of scripting, SVA, UPF validation.

  • Knowledge of JTAG and DFx is desirable.

  • Experience with advanced verification techniques such as formal and assertions a plus.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Folsom;US, Massachusetts, Hudson


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-03 Expires: 2022-06-03

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IP Logic Validation Engineer

Intel
Hillsboro, OR 97123

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