15 days old

Lead Design Verification Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0216209
Job Description

The Custom Structured ASIC Engineering Group within Intel Programmable Solutions Group is seeking a versatile and talented candidate to be part of Intel's next generation Custom Structured ASIC Development Team.


In this position you will be responsible for technically leading the Design Verification efforts on our Structured ASIC Platforms. This role requires in depth knowledge in one or more areas such as: SOC Verification Strategies, DFT, Debug, Boundary Scan, Emulation Platforms and High-Speed Interconnect Bus Architectures.
 

The candidate is expected to define the Verification Plan, develop tests for the critical blocks or 3rd party IP Integration and review the implementation of other tests with the team.

Essential Functions:

  • Define the Verification Plan and review the planned tests with the Design Engineering Team to make sure all use cases are covered.

  • Architect the Full Chip Verification Environment making sure all agents and drivers are implemented and reusable for future similar devices.

  • Work with Firmware Developers to create testcases targeting the critical functions of each subsystem.

  • Develop a regression system to support automated running of all implemented tests.

  • Work with Firmware and Design Teams to qualify end-to-end Device Configuration flow.

  • Work with the HW Emulation Team to identify additional areas of coverage which are difficult to achieve through standard UVM methodologies.

  • Improve the verification methodology by moving time consuming tests into the Emulation Platform reducing the overall regression runtime.

  • Define test scenarios for DFT Configuration and review with the ATPG Team that all modes can be enabled and used as expected.


Qualifications

Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

5+ years of relevant experience, experience should include:

  • Chip Design and Verification Flow.

  • Experience in System Verilog, VMM, UVM or OVM Based Verification Environments.

  • One or more scripting languages like Python, TCL or PERL.

Preferred Qualifications

Experience in one or more of the following is considered a plus

  • 10+ years of relevant experience.

  • Experience with Debug Interfaces (mainly JTAG).

  • Experience with different CPU Architectures.

  • Experience developing Firmware Driven Testbenches to validate SOC features.

  • Experience with Emulation Platform based testing.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-12 Expires: 2022-06-12

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Lead Design Verification Engineer

Intel
San Jose, CA 95113

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