14 days old

Logic Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0218683
Job Description

The world is transforming - and so is Intel! Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful!

In this position, you will be a member of the Design team working on the next generation Power Management IP. You'll work with Micro-architects and Architects to implement logic functional units in RTL, collaborate with Verification engineers to validate the design and take it through all the standard Design tools - eg synthesis/Formal Equivalence Verification/Clock Domain Crossing Verification - to deliver a high quality design. You will also be involved in functional and power simulations and debug.

Responsibilities will include but are not limited to:

  • Convert Architecture specification to Micro-architecture specification, implement logic functions in RTL using Verilog/System Verilog
  • Communicate/Coordinate effectively with validation, design and architecture teams
  • Test design using formal verification tools and functional verification environment
  • Qualify design to meet power, performance requirements using power simulation and static timing tools
  • Work with Pre/Post-silicon verification teams to debug and root-cause RTL simulation/Silicon/FPGA failures
  • Provide support to SOC customers for IP integration
  • Participate in the debug of customer issues and silicon sightings
  • Write scripts to automate design tool flows as required to improve efficiency

You will also have:

  • Problem solving Skills even in an ambiguous environment
  • Strong Written and Verbal Communication Skills
  • Ability to Work in a Dynamic Team Oriented Environment


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering or Computer Engineering with 3+ years of industry experience -OR- Master's Degree in Electrical Engineering or Computer Engineering with 2+ years of industry experience -OR- PhD in Electrical Engineering and/or Computer Engineering with:

  • Verilog, System Verilog
  • Logic Design, RTL Design
  • Knowledge of Design Tools and Design Analysis such as Design Compiler, CDC (Clock Domain Crossing), Closing Timing Violations
  • Scripting experience in languages like Python, Perl etc


Preferred Qualifications:

  • Power Management IP, Power Management SoC, DFX knowledge is a plus
  • Formal Verification Tools

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-04 Expires: 2022-06-04

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Logic Design Engineer

Intel
Santa Clara, CA 95050

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