As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

About the role:

• As Mask Designer in the PDK Validation team you will support validation and release of PDK custom layout and custom reliability collaterals to Intel internal design and IFS customers.
• Implement custom analog layout testcases on leading Intel technology nodes
• Work closely with the PDK development and QA team members and EDA suppliers to implement robust QA checks and resolve tool and collateral issues prior to PDK releases.

Important behaviors traits:

• Work independently with team members
• Share tool knowledge
• Problem solving skills
• Able to own schedule and project commitments and provide status updates to project leads

Qualifications

Minimum Qualifications:

9+ years of direct mask layout industry work experience

Preferred Qualifications:

• AA degree in VLSI or Physical Design/Mask Design.
• Experience with layout of the standard cells for APR, custom standard cell library, scribe layouts, and runset regression test cases
• Experience with industry-based (CAD) layout tools including Cadence (Virtuoso, VXL).
• Experience in verification (ICV/Calibre DRC, and LVS).
• Experience of basic electronic circuit functionality and behaviors (passive and active circuit structures).
• Experience layout section/FUB lead experiences.
• Experience in analog design and layout guidelines (matching devices, symmetrical layout, signal shielding, other analog specific guidelines).

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.