The DPEA/MIO - Memory Technology and Standards group is looking for an experienced memory architect to join our memory pathfinding and engineering team, in the field of client memory architecture development. Come join the inventors driving next generation standards and technologies and work directly with the memory architecture team that's helped shape many generations of memory standards in the industry.

This position provides an exciting opportunity to become a member of the Memory and IO Technologies team (MIO) in Data Center Platform Engineering (DPEA) and be at the driving seat to help shape the next generation memory technologies and standards (next generation DDR solutions, next generation LPDDR and beyond). As a memory architect you will work with Intel's MIO team that defines the standards for Intel's most strategic technologies and interfaces (DDR4/5, HBM, CXL, PCIe, USB, UPI) and will have a dual role and unique opportunity to collaborate closely with Intel's client architecture team advancing next generation mobile and desktop systems.

As a memory architect you will be responsible for but not limited to:

• Memory research and pathfinding initiatives for next generation memory technologies for client computing
• Co-definition of client computing memory requirements to ensure advancement of next generation memory technologies and standards
• Forming memory architecture and technology proposals that best match the generational client computing requirements
• Driving a holistic set of requirements to implement and validate new technologies
• Specifications and standards development
• Success in leading complex technical projects

The ideal candidate should exhibit the following behavioral traits:

• Willing to work with teams comprised of a diverse set of disciplines and geographies
• Exhibit a collaborative mindset
• Be self-driven
• Tolerance for ambiguity and working on open-ended problems

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Qualifications

You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications

• Minimum Education Requirement: Bachelor's Degree in Electrical Engineering
• 10+ years of experience working in the memory or SoC/CPU architecture field
• SoC/CPU or client system architecture and implementation (ideally with post-silicon validation experience)

Preferred qualifications

• Experience in Memory technology/DRAM and with industry standards
• Master's Degree in Electrical Engineering

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, California, Folsom;US, California, Santa Clara;US, Massachusetts, Hudson

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.