17 days old

Memory Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

You will be part of Intel Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools

As a member of this team, your responsibilities include (but not limited to):

  • Memory bitcell, array construction, and periphery IC physical design definition, pathfinding, and automation.
  • Memory library development and validation for PDK enablement across Intel's advanced process technologies.
  • Power performance area (PPA) optimization through design technology co-optimization (DTCO).
  • Memory array/IP design, memory circuit innovation, testchip design/execution/validation.


Minimum Education level:
MS degree in Electrical Engineering, Computer Engineering or a related discipline with 2+ years of professional experience in the following:

  • ASIC design flow and validation
  • CAD tools/flows for digital and/or analog design
  • CMOS custom circuit design, simulation, layout design and verification

Preferred Qualifications:

  • Design, characterization and verification of custom memory (SRAM, Register File, ROM) circuits
  • Physical design optimization on complex custom circuits
  • Design trade-off of power, performance and area
  • Design technology co-optimization

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-08 Expires: 2022-06-08

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Memory Design Engineer

Hillsboro, OR 97123

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