The DPEA/MIO - Memory Technology and Standards group is looking for an experienced memory architect to join our memory pathfinding and engineering team, working to define and enable memory subsystem solutions for both client and enterprise platforms. Come join the inventors driving next generation standards and technologies and work directly with the memory architecture team that's helped shape many generations of memory standards in the industry.

This position provides an exciting opportunity to become a member of the Memory and IO (MIO) Technologies team and be a core team member driving the definition of next generation memory technologies and standards (next generation DDR solutions, next generation LPDDR and beyond). As a memory architect you will work with Intel's MIO team that defines the standards for Intel's most strategic technologies and interfaces (DDR4/5, HBM, CXL, PCIe, USB, UPI) and will have a dual role and unique opportunity to collaborate closely with Intel's client and server architecture team advancing next generation platforms.

As a memory architect you will be responsible for but not limited to:
Memory research and pathfinding initiatives for next generation memory technologies
Co-definition of computing memory requirements to ensure advancement of next generation memory technologies and standards
Forming memory architecture and technology proposals that best match the generational computing requirements
Driving a holistic set of requirements to implement and validate new technologies
Specifications and standards development, including interfacing with memory ecosystem partners and standards bodies
Success in leading complex technical projects

Demonstrated experience debugging issues and making recommendations for remediation
Additional Skills
Willing to work with teams comprised of a diverse set of disciplines and geographies
Exhibit a collaborative mindset
Be self-driven
Tolerance for ambiguity and working on open-ended problems

Qualifications

Minimum qualifications
Bachelor's Degree in Electrical Engineering or related field and 10+ years of relevant experience

6+ years of experience in Memory design RTL or other Functional Model development

Preferred Qualifications

10+ years of experience working in the memory or SoC/CPU architecture field

5+ years of experience with DDR4/5 and LPDDR4/5 memory subsystem operation

Experience engaging with JEDEC standards body, and developing/sponsoring ballot proposals
SoC/CPU or system architecture and implementation (ideally including post-silicon validation experience)

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, California, Folsom;US, California, Santa Clara

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.