17 days old

Memory Electrical Validation Engineer

Folsom, CA 95630
  • Job Code
Job Description

The Memory and I/O Technologies Team, (MIO) is excited to announce an opportunity within the Intel Datacenter and AI Group. MIO works to define and validate DRAM memory and IO technologies for Intel, and we have an exciting Electrical Validation opportunity in Folsom, Santa Clara or Hillsboro, Oregon.

The qualified candidate would collaborate with engineering teams in Intel and in the DRAM industry, to develop the next generation of memory test tools used for post-silicon electrical validation of DDR5 memory in systems. Should you join our team, you would be working on the cutting edge of DRAM testing with experts at Intel and in the memory industry.

Our team members are passionate about growth, innovation, and collaboration and we are looking for individuals who want to learn and grow, so we can best support our customers with the highest quality possible. If you have a growth mindset and thrive in an engineering environment, you could be a great fit for our team.

On any given day in our development labs, you would test DRAM memory on Intel's platforms using the latest in electrical validation equipment such as logic analyzers, oscilloscopes, and bit error rate testers (BERT), collect data across platforms and memory technologies, assess results and collaborate with engineering teams to drive improvements. Be excited by continuously keeping up to date on emerging electrical validation test methods.

The ideal candidate should exhibit the following behavioral traits:

  • Excellent interpersonal, written and verbal communication skills.
  • Highly motivated individual willing to work under pressure and deliver high quality results on time.
  • Problem-solving and analytical skills.
  • Effective prioritization and time management skills.
  • Stakeholder management, strong collaboration, tolerance for ambiguity and critical thinking.
  • Excellent teamwork ethics.
  • Willing to work in an agile work environment with a fast-paced task flow.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a positive factor in identifying top candidates. Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum qualifications:

-The candidate must have a BS or MS degree in Electrical Engineering, Electronics Engineering, Mechatronics, Computer Science, Computer Engineering or related field.

3+ years of experience in some of the following areas:

-Logic analyzer, oscilloscopes, Bit Error Rate Tester (BERT) and/or other Electrical Validation (EV) test equipment.

-Python and/or C/C++.

-Debug and/or signal integrity.

Preferred qualifications:

-Experience with power delivery simulation (e.g. HSPICE, HFSS).

-Experience with DDR Memory.


Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-04-28 Expires: 2022-05-29

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Memory Electrical Validation Engineer

Folsom, CA 95630

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