25 days old

Mixed Signal Design Engineer (SK)

Folsom, CA 95630
  • Job Code
Job Description

As an Mixed Signal Design Engineer will be responsible, but not limited to:

  • NAND digital and analog design with respect to chip level integration. Analysis of timing, layout, and voltage domain crossings/constraints.
  • Work with teams on full chip block placement and optimizations (including design) for block level and full chip routing.
  • Power modeling and defining inventive methods for power reduction.
  • Analysis of Simulation to Silicon performance and continuous improvements in tool flow and modeling.
  • Improving DA tools and methodologies for Spice, Primetime, active current analysis, 3-d coupling, and analog/digital routing based on efficiency and accuracy.
  • Work with TD (modeling and FAB) to improve interconnect and devices needed to meet higher performance requirements with power reduction.
  • Work with DE and Layout to define full chip routing for various high and low voltage domains and critical nets.
  • Review Static R and other reports to fix layout problems and prepare for high quality tape release.

This position is associated with the sale of Intels NAND memory and storagebusiness to SK hynix (You can read more about the transaction in the press release - https://newsroom.intel.com/wp-content/uploads/sites/11/2020/10/nand-memory-news-q-a.pdf). The transaction will enhance the resources and potential of the business storage solutions, including client and enterprise SSDs, in the rapidly growing NAND Flash space amid the era of big data.  

This is an exciting time to be at Intel come join our team as a Mixed Signal Design Engineer and work on one of the most advanced 3DNAND and SSD technology portfolios in the world. As the global leader in the semiconductor industry, Intel possesses many industry-leading SSD technologies including the most capable Quadruple Level Cell (QLC) NAND Flash products. As a Mixed Signal Design Engineer, you will be part of a world-class team that will transition to lead the SSD business at SK hynix.  

Candidates being hired for Phase 2

This position aligns to Phase 2 of the transaction, which includes NAND technology and component development along with fab operations. Employees aligned to Phase 2 will continue to be employed by Intel and will continue to develop NAND technology and components and manufacture NAND wafers at the fab. Phase 2 of the transaction is expected to close in March 2025, at which time employees aligned to this phase of the transaction will transition employment to SK hynix. 


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical Engineering, Computer Engineering or related field.
8+ years of experience in the following areas:

  • Analog/Digital circuit design to pre/post-silicon validation to product qualification.
  • Layout design rules and layout optimization (DC/LVS debug).
  • Coupling, crosstalk delay, effects of process variation, and clock insertion delay effects on timing margins and analog circuit performance.
  • SPICE simulation, and willing to adapt to new simulation tools.
  • EDA tools, Design Compiler, ICC2, Primetime and in transistor level analog/mixed signal circuit design.

Preferred Qualifications:

A Master's degree with 6+ years of experience in the minimum qualifications

4+ years of experience in the following areas:

  • Logic cells used Cell library development and custom logic. RAM ROM design and timing models, timing closure analysis, and circuit tradeoffs used to fix timing problems.
  • Power simulations and power reduction methods.
  • Circuit reliability tools and methodologies such as EM/IR, aging, noise, margin, and high sigma variation simulations.
  • Programming and scripting languages.

Inside this Business Group

Employees in Intel's NAND Product Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-02 Expires: 2022-06-02

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Mixed Signal Design Engineer (SK)

Folsom, CA 95630

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