9 days old

Mixed Signal Layout Engineer, Intel Foundry Services

Intel
Santa Clara, CA 95050
  • Job Code
    JR0219428
Job Description

Intel IFS is seeking an experienced, self-driven layout designer with proven skills in physical layout of sensitive analog, digital, and mixed-signal circuits. This position will require floor planning, detailed sensitive signal routing and sensitive logic layout techniques. Support and collaboration with Analog and Digital Designers, peers and global teams is essential to successfully complete circuit layouts and meet schedules.

This layout position requires you to work well in a team environment and collaborate effectively with others, and to debug and resolve layout related issues to find solutions. You will produce custom layouts of analog circuit designs in Virtuoso, following analog layout techniques for sensitive physical layout considerations. You should demonstrate a strong understanding of how your physical layout will be integrated into the full product environment and implement layout requirements for all precautionary and protective steps, to ensure proper function of the macro in full chip.

In addition, you will be working on Static Timing Analysis (STA) flows related to constraints development, timing analysis and timing closure, SI crosstalk, glitch analysis, on-chip variation, etc., to ensure accuracy, while maintaining performance, reducing turnaround times, and using compute resources efficiently. Timing constraints development and validation are other key areas, where your role will be critical to ensure the success of our chips. You will also contribute to timing closure of designs from blocks to full chip by working with team members in Logic Design, Analog Design, Design For Test (DFT). Strong scripting skills are required to be successful in this role.

Responsibilities include - Synthesis, UPF development, Timing Constraints development, timing constraints validation, formal equivalence checking, Floor planning, power grid design, place and route, signoff Static Timing Analysis and full-chip and block-level timing closure.

The ideal candidate should exhibit the following behavioral traits:

  • Clarity in technical communications, ability to partner with design engineers to achieve efficient circuit performance
  • Results oriented self-starter with the ability to work independently, and an aptitude for hands on problem solving
  • Collaboration skills with the ability to align diverse stakeholders and resolve conflicts
  • Proactive response to issues impacting productivity and workflow to resolve roadblocks
  • Coordinate, conduct and lead layout reviews with peers and Analog Design teams. Have strong understanding of sensitive logic and signals, prune plots and provide visual examples of how logic was drawn


Qualifications

You must possess the below minimum qualifications to be initially considered for this position.

Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Associates or Bachelor's degree in Electronics, Electrical Engineering, Computer Engineering, or Computer Science or related discipline
  • A minimum of 2 years experience in custom analog layout, digital auto-place and route, or mixed signal CMOS layout
  • Experience with Cadence tools or other tools used to deliver physical layout designs, precision analog layout techniques, and physical layout verification
  • Experience with Place and route tools, any one or more of ICC2, Fusion compiler, Cadence Innovus or similar


Preferred Qualifications:

  • Understanding and progressed experience level with physical layout techniques used in extremely sensitive circuits; LDO, BUCK, bandgap voltage reference, ADC, DACs, Oscillators, etc.
  • Experience with advance layout in Foundry technologies
  • Knowledge of synthesis flow
  • Expertise with industry leading STA and timing ECO tools such as PrimeTime
  • Knowledge of multi-voltage implementation
  • Experience and understanding of layout methodology from initial floor planning to release.
  • Experience in Tcl and Perl/Python programming.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Oregon, Hillsboro;Virtual US and Canada


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$97,230.00-$160,990.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.


Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-09 Expires: 2022-06-10

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Mixed Signal Layout Engineer, Intel Foundry Services

Intel
Santa Clara, CA 95050

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