2 days old

NAND SPICE Modeling Engineer (SK)

Intel
Santa Clara, CA 95050
  • Job Code
    JR0206442
Job Description

Come join our team as a NAND SPICE modeling engineer!

What you'll do:

  • Be responsible for characterizing device behavior and generating device models for NAND technology, implementing device models into the PDK, and ensuring robustness and accuracy of model simulation.
  • Define device specs and determine the best usage of the device type/sizes and device models in circuit design, together with the device team, reliability team, and design team.

The ideal candidate should demonstrate the following behavioral traits:

  • Demonstrated leadership skills in defining model development roadmap and aligning goals with the design/ TD requirements.

  • Must be able to operate in a matrix environment with multiple priorities and deadlines.

  • Great communication skills.

  • Team Player.

The position is associated with the sale of the NAND business to SK Hynix aligning to Phase 2 of the transaction. Employees aligned to Phase 2 will continue to be employed by Intel developing NAND technology and components. Phase 2 of the transaction is expected to close in March 2025 at which time employees aligned to this phase of the transaction will transition employment to Solidigm, a stand-alone US subsidiary of SK Hynix headquartered in San Jose, California with offices worldwide. Solidigm is a leading global supplier of NAND flash memory solutions, led by Robert (Rob) B. Crooke as CEO, previously senior vice president, and general manager of Intels Non-Volatile Memory Solutions Group. To read more, see: https://www.intc.com/news-events/press-releases/detail/1513/intel-sells-ssd-business-and-dalian-facility-to-sk-hynix


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications:

  • A Master's degree in electrical engineering or related discipline.

  • A minimum of 4+ years of direct experience in the following with CMOS, interconnect modeling, and characterization.

  • Must have a background in semiconductor device physics, design, and layout of structures for parametric extraction.

  • Understanding of basic analog / digital circuit blocks and model interaction.

  • Experience in BSIM3/4 models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators (example: HSPICE, SPECTRE, etc.).

  • Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems. Experience in test automation and reliability tests is a plus.

  • Hands-on experience in C, C++, and/or Python programming.

  • Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.

  • Understanding of Aging Simulations and reliability methodologies and tools.

Preferred Qualifications:

  • A Ph.D. degree in electrical engineering or related discipline with a minimum of 2 + years of experience in the minimum requirements and the following:

  • Direct experience in the following with CMOS, interconnect modeling, and characterization.

  • Must have a background in semiconductor device physics, design, and layout of structures for parametric extraction.

  • Understanding of basic analog / digital circuit blocks and model interaction.

  • Experience in BSIM3/4 models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators (example: HSPICE, SPECTRE, etc.).

  • Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems. Experience in test automation and reliability tests is a plus.

  • Hands-on experience in C, C++, and/or Python programming.

  • Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.

  • Understanding of Aging Simulations and reliability methodologies and tools.

  • NVM (NAND/ Emerging memory) experience is strongly preferred but not required.

Inside this Business Group

Employees in Intel's NAND Product Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.



Other Locations

US, California, Folsom


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-17 Expires: 2022-06-18

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NAND SPICE Modeling Engineer (SK)

Intel
Santa Clara, CA 95050

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