We're looking for Novel Memory Circuit and IP Designers! These memory arrays are used for both technology development and also Product IP.

About the role:

Job requires schematic drawing, pre and post layout Spice simulations, Timing validation using tools such as Primetime. It also requires validating the design for Electro Migration, and transistor Aging. Experience in Memory IP Delivery is a plus, such as generating .Lib files with Power attributes etc. for customer integration

About our organization:

Advanced Design (AD) Group under Design Enablement in Technology Development has primary focus of Design Technology and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams.

Results of our innovative, high-quality and exciting memory design and development work are published at prestigious conferences and journals, as well as many patents issued. Following are few examples of these publications from our group:

• Liqiong Wei et al., A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique, ISSCC Dig. Tech. Papers, Feb. 2019.
• Pulkit Jain et al.  A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V, ISSCC Dig. Tech. Papers, Feb. 2019.
• Fatih Hamzaoglu et al. A 1Gb 128GB/s Bandwidth Embedded DRAM in 22nm Tri-Gate CMOS Technology, IEEE J. Solid-State Circuits, pp. 150-157, Jan. 2015
• Mesut Meterelliyoz et. al. 2nd Generation Embedded DRAM with 4X Lower Self Refresh Power in 22nm Tri-Gate CMOS Technology, IEEE Symp. VLSI Circuits, June 2014

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

MS degree in EE or related field with 2+ years of processional/ work experience or PhD degree in EE or related field with academic work experience.
Experience in the following:

• Custom circuit design
• EDA Timing, Schematic, Layout and RV tools
• RTL and synthesis of digital blocks.

Preferred Qualifications:

• Memory Circuit and IP Design
• Memory IP Delivery, If candidate has owned delivering SRAM or Register File IP Collaterals to Customers

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.