This is an exciting time to be at Intel - come join our NAND Collateral Team as an OPC engineer and work on one of the most advanced 3DNAND and SSD technology portfolios in the world. As the global leader in the semiconductor industry, Intel possesses many industry-leading SSD technologies including the most capable Quadruple Level Cell (QLC) NAND Flash products. As an OPC engineer, you will be part of a world-class team that will transition to lead the SSD business at SK hynix.

The Intel NAND-DTM Process Technology Development group is responsible for developing state of the art 3D-NAND technology. As a NAND collateral development engineer, you will be responsibilities will be in the areas of initial tape-out reviews, verification of design rules, generation of rules, or model-based mask flows and mask-ready data, and verification of this data to DRs or fab needs. The final goal is alignment between Litho process, mask and OPC to deliver the right patterns on the wafer. The specific functions of an OPC engineer are to define OPC solutions for new layers or challenging design rules on new nodes including illumination, SMO, resist models, etch models, target layer definition, OPC recipes, OPC checking and fab verification. The ideal candidate will have: Demonstrated willing to produce effective, efficient and flexible code to spec along with user interfaces and documentation.

This position is in the NAND-DTM Group which is aligned to phase 2 of the sale of the NAND business to Solidigm, a wholly owned subsidiary of SK hynix. Employees in this business group will work on developing NAND technology and components.  Phase 2 of the transaction is expected to close in March 2025 at which time employees aligned to this phase of the transaction will transition employment to Solidigm.  Solidigm, a leading global supplier of NAND flash memory solutions, is headquartered in San Jose, California with offices worldwide.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:
Master's degree and 3+ years with relevant academic or industry experience
3+ years of experience in semiconductor industry or relevant academic endeavors
Experience with Tape-out, OPC and Mask Generation Flows for High volume manufacturing or Technology Development
Experience with of Calibre, any OPC software platform or any other languages like Python, C, C++ in Linux.

Preferred Requirements:
PhD degree with relevant academic or industry experience

2+ years of experience in the following areas:
Semiconductor device and layout.
Device physics and parametric analysis.
Photolithography and reticle creation.
OPC and manipulation of incoming data to create mask images to construct desired shapes in resist on silicon wafers
CAD tools and software such as Mentor, Cadence, and Synopsys tools
Wafer fab processes with focus on Litho module and optimizing illumination details to design rules and OPC.
Linux operating systems and batch job controls and monitoring.

Employees in Intel's NAND Product Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.