19 days old

Package Design Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0215518
Job Description

Intel is a global leader, creating world-changing technology that enables progress and enriches lives. We are at the intersection of several technology inflections artificial intelligence, 5G network transformation and the rise of the intelligent edge- that together will shape the future of technology. 

As part of Intel, Programmable Solutions Group (PSG) creates market-leading programmable logic devices that deliver a wider range of skills than customers experience today. Combining industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing skills will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency.

PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative and allows our employees to reach their full potential.

In this role, the successful incumbent will develop next generation package solution from concept till tape-out. Ensure the package solution meets requirement for quality, performance, and cost. Manage multiple designs concurrently, working with multi-disciplinary teams. Leading the package design efforts for the development of pin map/ball map, in collaboration with the Package Architect, Design Lead, Designer, Power Integrity, and Signal Integrity engineers. Perform package design work such as package size fit assessment, package stack-up study, design rule to HVM, package signal and integrity requirement, new IP design and ball pattern assessment, drive package module design creation. Optimize package layout include ball map/bump map, stack-up and design methodology.

Additional responsibilities include, but not limited to:

  • Driving the substrate physical design reviews as per plan and meet the schedule and quality expectations.

  • Validating the design using design validation tools.

  • Ensure timely release/tape out of cost optimal high quality package substrates, after reviews with internal stakeholders and with the package substrate manufacturing vendors.

  • Perform package design work per business process from layout to documentation. Manage package design related issue and highlight to Package Architect and SIPI Lead.

  • Follow up closely to close the design issue. Leading the path finding assessment and handover good quality deliverable to design execution team for design start.

  • Identifying areas for improvement, for example: design tool features, design efficiency, design methods, and proactively seeking to partner with experts/teammates to drive the improvements.

  • Innovative solutions for continuous improvement in efficiency and throughput.

  • Providing inputs to the substrate and package assembly technology development teams to enable development of industry-leading designs.

  • A team player, strong problem solver, highly motivated, self-directed, and should be willing to work effectively, both independently and with other team members.

This position is not eligible for Intel sponsorship.


Qualifications

Educational requirements:

  • HS Diploma or equivalent .

Minimum Requirements:

  • Experience in design tool experience such as Siemens Mentor Xpedition, Xpedition Substrate Integrator, and Cadence APD.
  • 5+ years of SOC, Flip-Chip package design and/or PCB Design or combined experience.
  • Experience in defining package solution would be an added advantage.
  • Experience with signal integrity and power integrity basics.

Preferred Requirements:

  • 10+ years of industry experience.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Folsom;Virtual US and Canada


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$113,210.00-$187,350.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.


Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

Posted: 2022-05-07 Expires: 2022-06-07

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Package Design Engineer

Intel
San Jose, CA 95113

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