14 days old

PDK Application Engineer - Physical Verification

Intel
Santa Clara, CA 95050
  • Job Code
    JR0205561
Job Description

About the Group:As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can choose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with Arm and RISC-V ecosystem IPs.If you have a strong technical background and like customer interaction, this is the position for you. Intel Foundry Services (IFS) Applications Engineering team is looking for independent, self-motivated candidates with strong technical skills in SOC/IP/ASIC design and methodology to work with our customers. As part of our IFS group, you will help drive IFS technologies and solutions into customer's engineering teams as well as be the customer advocate working back with internal development teams. You will ensure Intel collaterals and services can continuously meet IFS customers' needs that would lead to successful chip tape-outs. Joining this group means you will be representing Intel enabling customers' satisfying experiences and eventual outcome, financial success. Opportunity to learn and expand your knowledge on various physical design domains is an additional benefit. In this role you will: Provide ongoing support, tight collaboration with internal development teams and EDA vendors on issue resolution, preparing and delivering technical training/presentations, knocking down all barriers to successful sub-22nm customer tape-outs. Collaborate with physical design domain experts, design and develop exploratory, automated Quality Assurance (QA) flow in IFS AE environment, enabling automation at various stages of testing - Integration, Functional testing, Regression, End-to-End (E2E) and User Acceptance Testing (UAT), to ensure Intel collateral quality improvement. Work with the QA analysts, add new usage models and testcases, either from customers or synthetic, to prevent recurring quality issues in Intel collaterals. Drive quality design kit content and its documentation delivered to customers. Promote customers use IFS Best Known Methods (BKMs).


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experienced listed could be a combination of relevant course work, internships or on the job experience.

Education Requirement:
Bachelor's degree in Electrical Engineering, Science, Computer Science, Engineering, or related field of stud with 6+ years of experience OR Master's degree in Electrical Engineering, Science, Computer Science, Engineering or related field of study with 4+ years of experience.

Minimum Requirements:

  • 4+ year experience in Physical Verification (PV) tool deck development/support, like Synopsys Integrated Circuit Validator (ICV), Siemens (Mentor) Calibre, and/or Cadence Pegasus
  • 6+ year experience in physical design (silicon IP/SOC/ASIC)
  • 6+ year experience in scripting languages like Python, Perl, Tcl, and/or shell scripting.
  • 10+ year experience with CMOS processes.


Preferred Qualifications:

  • Hands-on experience and knowledge in various types of PV checks (LVS, DRC, DFY/DFM, lithography) at the chip/block level or chip tape-out experience with a track record of successful signoffs.
  • Knowledge of hierarchical design approach, top-down design, budgeting, timing and physical convergence, DRC correlation with APR tool, and building Quality Assurance (QA) regression test suite.
  • Programming experience in Python, Perl, Tcl, or other equivalent scripting language, including but not limited to flow-related issue debug/fix, new solution/enhancement development, productivity/quality-increasing automation, etc.
  • Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies and BKMs to streamline physical design work, speccing guidelines and checklists, driving execution, and tracking progress while offering physical verification support.
  • Knowledge of adjacent physical design flow domains, like layout design, fill, parasitic extraction.
  • Practical experience with one of the IaaS public cloud offerings (MS Azure, Amazon AWS, Google) in semiconductor design/EDA Virtual Design Environment (VDE).

Inside this Business Group

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-13 Expires: 2022-06-13

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PDK Application Engineer - Physical Verification

Intel
Santa Clara, CA 95050

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