26 days old

PDK customer support for Physical Layout Verification

Intel
Phoenix, AZ 85003
  • Job Code
    JR0215947
Job Description

About our organization

This position is within the Design Enablement (DE) which is one of the key pillars enabling Intel to deliver winning products in the marketplace. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

About the role

The Process Development kit (PDK) Customer Support team within this organization is looking for Customer Obsessed individual in the area of Physical Layout Verification support to provide a positive experience to our customers. The candidate would be expected to help resolve the customer issues they see while using the PDK collateral in physical layout verification tools. In addition, the candidate would prepare training material to inform and educate customers on PDK collateral usage.

The successful candidate should exhibit the following behavioral traits:

  • Proven track record of uncompromising customer orientation to deliver leading-edge solutions
  • Debugging skills to root cause the customer issue and propose solutions
  • Be fearless in bringing the voice of the customer to the PDK team and ability to lead and facilitate meetings with customers and PDK team to ensure timely resolution of customer issues
  • Thrive in a fast paced, challenging environment
  • Detail oriented
  • Verbal communication, technical writing skills, and presentation skills.


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:

Bachelor of Science in Electrical Engineering, Computer Engineering, or relevant scientific STEM major with 4+ years of professional experience or MS with 3+ of professional experience in the following areas:

  • Physical layout verification knowledge in at least one of the following: Synopsys IC Verification, Siemens/Mentor Calibre
  • Resolving DRC/LVS/density issues
  • Process layout design rule from DRM (Design Rule Manuals)
  • Runset development

Preferred:

  • Intel and/or external foundry process technology knowledge in advance nodes

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, California, Folsom;US, California, San Jose;US, California, Santa Clara;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-01 Expires: 2022-06-01

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PDK customer support for Physical Layout Verification

Intel
Phoenix, AZ 85003

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