20 days old

Physical Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

Be part of Design Enablement/ LVD: Lead Vehicle Development group, where you will join a highly motivated team of talented engineers who design and execute test chips to support all stages of process technology development, they define test chip content that enables yield and performance tracking and add value that enhance speed and quality of yield and debug learning, providing benchmark circuits to monitor and evaluate process maturity.

As Physical Design Engineer, youll be responsible for but not limited to the following:

  • Creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, FUB level floor plans
  • Abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full chip assembly, packaging, and verification.
  • Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
  • Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
  • Requires expansive knowledge and practical application of methodologies and physical design.

This position does not qualify for Intel Sponsorship because it is either (1) a non-STEM contributing position, or (2) a STEM position that only requires a bachelors degree and less than three years experience. 


You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ years experience with the following:

  • Electronic circuit functionality and behaviors
  • Component design principles
  • Complementary Metal-Oxide Semiconductor (CMOS)
  • Very Large-Scale Integration (VLSI)

Preferred Qualifications:

  • Custom layout design skills (SRAM, Register File, Analog)
  • Hierarchical Layout planning and integration skills.
  • Programming skills at least of these: Tcl, SKILL, Perl, Python
  • ICV/Calibre runset verification flow skills.
  • Knowledge of CAD layout software (Cadence Virtuoso VXL and ICC2 layout tools)
  • Knowledge in Unix/Linux operating systems

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Arizona, Phoenix

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-05 Expires: 2022-06-06

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Physical Design Engineer

Hillsboro, OR 97123

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