11 days old

Physical Design Engineer Manager

Intel
San Jose, CA 95113
  • Job Code
    JR0205354
Job Description

Intel's Programmable Solution Group (PSG) is responsible for designing the state-of-the-art FPGAs/SoCs. We envision the future of computing and design for the next generation in many vertical domains such as Wireline, Wireless, Data Centers, etc.

Our bold purpose as a company is to "create world-changing technology that enriches the lives of every person on earth" and this role is instrumental in furthering our mission to shape the future of technology. Our team is looking for a Physical Design Engineer Manager and in this role you will:

  • Set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.

  • Oversee definition, design, verification, and documentation for SoC (System on a Chip) development.

  • Determines architecture design, logic design, and system simulation.

  • Define module interfaces/formats for simulation.

  • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.

  • Perform all aspects of the SoC design flow from synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

  • Review vendor capability to support development (if applicable).

  • Select, develop, and evaluate SoC design engineers to ensure the efficient operation of the function.

Your scope of responsibilities may include, but not be limited to:

  • Design Constraints (SDCs) Creation/Cleanup/Verifications

  • Timing (STA) Closure at various Levels (Block/Sub-system/Full-chip)

  • Power Closure at various Levels (Block/Sub-system/Full-chip)

  • TECO (Timing ECO) Flow/Methodology/Execution

  • DFT structure/Scan Chains

  • Synthesis/Scan-Insertion

  • General PD Debugging (placement/CTS/routing)

  • SoC Design integration Methodology - RTL2GDS, Clock design Methodology, Power delivery, Performance Verification

  • Static timing analysis, constraint understanding, generation, clock stamping, and timing closure Multiple Power Domain analysis using standard Power Formats UPF/CPF Place and Route and clock tree synthesis, Design signoff and hand off to the Mask Shop.


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

10+ years of total experience, experience should include:

  • Physical design (timing closure, power closure and/or physical integration/signoff).

  • Multiple Tape-out experience (RTL to GDSII) including 2-3 tape-outs in latest technology.

  • Experience with physical design industry standard EDA tools such as ICC2, DC (Design Compiler), Fusion Compiler (FC), Primetime (PT/PT-SI/PT-PX), Apache/Ansys Redhawk/Totem, Siemens/Mentor Calibre, Cadence Conformal/Synopsys Formality

Preferred Qualifications

One or more of the following is considered a plus factor

  • Experience with complex ASIC/SoC Tape-out (10-15M+ Standard Cells with 1GHz+ Performance Target).

  • Previous/current People/Technical Management experience.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-05-14 Expires: 2022-06-14

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Physical Design Engineer Manager

Intel
San Jose, CA 95113

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