29 days old

Physical Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

In this position you will be part of a world class Ethernet IP & SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team.  You will perform all aspects of the physical design flow from engaging with design team through synthesis, place and route, timing analysis and power reduction.  This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.


Responsibilities will include but not limited to:

- Drive technical activities during all phases of physical design execution.

- Work extensively with SoC and RTL teams to help optimize/converge the designs to achieve the best Power, Performance, and Area (PPA).

- Ensure cross geos and cross-functional teams communication Sub-Chip level and block-level floor planning with Power supply and power grid planning and analysis.

- Logic synthesis of design blocks, Formal Equivalence Verification (FEV).

- Clocking network planning and analysis, Auto Place-and-Route (APR) using Synopsys ICC tools / Cadence Innovus tools.

- Timing signoff and timing ECO using Synopsys Prime Time, Physical verification - Layout vs. Schematic (LVS).

- Design Rule Checks (DRC), Electrical Rule Checks (ERC)Eager to improve, influence tools, flows and overall RTL to GDS physical design methodology with data-drive approach. 


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Education Requirement:

- Bachelor's degree in Computer science/Electrical or Computer Engineering with 10 plus years of experience.

Minimum Qualifications:
- 5+ years of experience executing on complex network SoC/ASICs.
- 5+ 5+ years of experience with Scripting using a programming language such as Perl, TCL, or Python.

Preferred qualifications:
- Master's degree in Computer science, Electrical or Computer Engineering with 7 plus years of experience.

- 5+ years of experience working on advanced process nodes such 7nm and below.

- 5+ years of experience with semiconductor device physics.

- 5+ years of experience with Physical Design and verification Tools, Flows and Methods.

- 5+ years of experience with physical design tools such as DC (Design Compiler), ICC2/Innovus, PrimeTime, etc.

- 5+ years of experience with Redhawk for signal EM and IR drop analysis.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Other Locations

US, Arizona, Phoenix

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-04-26 Expires: 2022-05-27

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Physical Design Engineer

San Jose, CA 95113

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