20 days old

Physical Design Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0214923
Job Description

Come and join us. Intel is seeking highly qualified candidates to join the XFG (Switch and Fabric Group) in our Network and Edge Group (NEX) as a Physical Design Engineer. We're part of the Connectivity Group (CG) in Intel's NEX, and are looking for motivated, passionate and talented engineers to join our Silicon Engineering team for programmable high-speed switching ASICs. We're a strong, vibrant, cross-site team that helps drive Intel's programmable switching technology and products to position Tofino as the switching platform of choice for Cloud and Data Center network deployments.


Qualifications

Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job relevant experience, internship experiences and or schoolwork/classes/research.

Education Requirements
Bachelor of Science in Electrical or Computer Engineering or related field plus 5 years of semiconductor industry experience.

Minimum Requirements
3+ years in physical design and experience on block closure.
3+ years of experience in floor planning and global timing verification, and Physical Design Verification Flows.
1+ years of experience with IR drop/EM analysis and developing guard bands for desired yield and performance.
2+ years of experience with SoC issues such as multiple voltages and clock domains, ESD strategies , low power design.

Preferred Qualifications
4+ years of experience in advanced package technologies
3+ years of experience with Hierarchical design approach, top-down design, budgeting, timing, and physical convergence
3+ years of experience with large SoC designs with power/performance upwards of 1GHz and die size challenges.
1+ years of experience in various process-related design issues, including Design for Yield and Manufacturability, multi-Vt strategies, and thermal management.

Benefits: Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intels benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, four-week paid sabbatical every four years of employment, family planning care including adoption and fertility assistance, and over 45 diverse employee resource groups for networking and advocacy.  Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.



Other Locations

US, Arizona, Phoenix;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-07 Expires: 2022-06-07

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Physical Design Engineer

Intel
San Jose, CA 95113

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